In this course, you use Encounter® Conformal® Equivalence Checker GXL for custom circuit equivalence checking. You learn to run abstraction of transistor circuits and memory circuits. Then, you set up and verify designs, analyze the results, and debug the abstracted designs against the gate-level design or the RTL.
After completing this course, you will be able to:
- Abstract transistor-level circuits
- Run equivalency checks between RTL and the abstracted logic designs
- Abstract memory circuit designs
- Create formally verifiable memory RTL
- Perform equivalency checks between RTL and the abstracted memory circuits
Software Used in This Course
- Encounter® Conformal® Equivalence Checker GXL
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- Basic Flow
- Abstraction Options
- Circuit Design Verification
- Memory Circuit Verification Flow
- Structure Accuracy Modeling: Test View
- Custom Circuit Designers
- Memory Designers
- Verification Engineers
You must have experience with or knowledge of the following:
- CMOS devices
- Layout design
- Logic Equivalence Checking with Encounter Conformal EC
Or you must have completed the following courses:
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