The Verilog Language and Application course offers a comprehensive exploration of the Verilog HDL and its application to ASIC and programmable logic design. The course provides a solid background in the use and application of the Verilog HDL to digital hardware design. This training course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification. It also touches upon ASIC library design concepts.
After completing this course, you will be able to:
- Use fundamental Verilog constructs to create simple designs
- Ensure that Verilog designs meet the requirements for synthesis
- Develop Verilog test environments of significant capability and complexity
Software Used in This Course
- Any Verilog simulator compliant with IEEE Std. 1364-2001
- Incisive 13.1, Encounter RTL Compiler 12.1
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
Day 1 and 2: Verilog Language Basics
- The first two days of the course cover the fundamental principles of the language and the constructs most commonly used in synthesizable Register Transfer Level (RTL) design.
- Problematic concepts such as blocking and nonblocking assignments are discussed in depth, and industry best-practice guidelines are presented.
- Course introduction
- Verilog applications
- Language introduction
- Logic system and data types
- Procedural statements
- Continuous and procedural statements
- Procedural statements and the simulation cycle
- Blocking and non-blocking assignments
- Functions and tasks
- Compiler directives
- Introduction to the synthesis process
Design and Synthesis Coding Styles
- The third day examines synthesis coding styles and guidelines in depth, including an explanation of the rules for writing high-quality, reusable, and synthesizable code.
- Definition of the RTL code
- Synthesis of mathematical operators
- Synthesis coding styles
- Advanced synthesis coding styles
- Designing finite state machines
- Avoiding simulation mismatches
- Verilog sample design
Advanced Constructs and Verification Issues
- Day four introduces additional language constructs and considers techniques and strategies for the functional verification of large-scale designs.
- Verification constructs
- Coding design behavior algorithmically
- System tasks and functions
- Generating a test stimulus
- Developing a Verilog testbench
- Application of Verilog testbenches
- Design Engineers
- Verification Engineers
You must have:
- The ability to navigate a file system and use a text editor
- A basic understanding of digital hardware design and verification
Prior experience with a procedural programming language is useful.
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