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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online Subscription Available 24 hours, 7 days a week.Online2800.00Register »
OnlineMMSIM13.1Available 24 hours, 7 days a week.Online  1575.00Register »
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Instructor LedMMSIM 13.1Scheduled upon demand 24  Hrs2100.00Express Interest »
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Virtual InstructorMMSIM13.1Scheduled upon demand 20  Hrs2100.00Express Interest »
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Course ID:  ES_82086_MMSIM 13.1

Course Description

In this course, you use the Virtuoso® Analog Design Environment and Virtuoso Spectre® Circuit Simulator to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You also learn to format output data and to use waveform filters to improve simulation performance. In this course, you also examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes.

Learning Objectives

After completing this course, you will be able to:

  • Determine the importance of top-down design methodology for accelerating complex system development
  • Write behavioral models of electrical circuits using the correct Verilog-A language and syntax
  • Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso Analog Design Environment and the command line
  • Verify that Verilog-A modules properly describe the intended function
  • Use software design tools to facilitate model development

Software Used in This Course

  • Virtuoso Analog Design Environment L
  • Virtuoso Spectre Circuit Simulator
  • Virtuoso Visualization and Analysis XL

Software Release(s)

  • IC 6.1.6, MMSIM 13.1

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • About This Course and Getting Help
  • Basic Modeling Concepts
  • Verilog-A Flow and Simulation
  • Design of Verilog-A Modules

Day 2

  • Verilog-A Modeling Descriptions
  • Analog Event Detection
  • Analog Operators and Filters
  • Verilog-A Functions and Operators

Day 3

  • Looping and Conditional Constructs
  • User-Defined and System Functions
  • Displaying and Printing Results
  • AHDL Linter Checks

Audience

  • Analog/Mixed-Signal Designers
  • IC Designers
  • Library Developers
  • System-level IC Designers

Prerequisites

You must have experience with or already have knowledge of the following:

  • Some programming, UNIX or Linux, a text editor

You must have completed the following courses:

You must have experience with the following software:

  • Virtuoso Analog Design Environment L
  • Virtuoso Spectre Circuit Simulator
  • Virtuoso Visualization and Analysis XL

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