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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online Subscription Available 24 hours, 7 days a week.Online2800.00Register »
Online16.6QIR8Available 24 hours, 7 days a week.Online  1575.00Register »
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Instructor Led201505 Oct 2015 - 06 Oct 2015Cadence San Jose > ES Training Room SJ316  Hrs2100.00Register »
Instructor Led201503 Dec 2015 - 04 Dec 2015Cadence Chelmsford > ES Training Room Groucho16  Hrs2100.00Register »
 More Instructor-Led
Instructor Led16.6QIR7Scheduled upon demand 16  Hrs2100.00Express Interest »
Instructor Led16.6Scheduled upon demand 16  Hrs2100.00Express Interest »
Virtual Instructor16.5Scheduled upon demand 16  Hrs2100.00Express Interest »
 More Virtual offerings

Course ID:  ES_86081VC_16.5

"The topics covered are very relevant; and it sparked some good discussion among the attendees which is great. The labs and instructions are very easy to follow, and being able to work with the tools hands-on help reinforce the learning. The Instructors have been very helpful in customizing and being flexible about the course material to fit our needs. It is a very admirable effort from them”
Satisfied Cadence Customer, Ericsson

Course Description

This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course.

In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs.

Learning Objectives

After completing this course, you will be able to:

  • Define specific net scheduling of high-speed nets
  • Match the propagation delay of nets and connections
  • Define minimum and maximum propagation delays for nets and connections
  • Identify high-speed constraint violations
  • Identify all the high-speed constraints that you can apply to the nets in your designs
  • Create spacing and physical constraints as well as area constraints and class-to-class rules
  • Customize worksheets
  • Create formula-based constraints
  • Create customized constraints using the SKILL® programming language

Software Used in This Course

  • Allegro PCB Design HDL
  • Allegro Design Entry HDL

Software Release(s)

  • SPB 16.5

Course Sessions

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Session 1

  • Database setup
  • User-defined net scheduling

Session 2

  • Propagation delay
  • Relative propagation delay
  • Impedance constraints

Session 3

  • Total etch-length constraints
  • System constraints
  • Physical and spacing constraints

Session 4

  • Formula-based constraints
  • Custom constraints


  • Logic Designers
  • PCB Designers


You must have experience with or knowledge of one of the following tools:

  • The Allegro PCB Editor, Allegro Package Designer, or Allegro Design Entry software

System Requirements for Virtual Courses

  • Click here for system requirements for attending a virtual course.

Related Courses

  • Allegro Design Entry HDL Front-to-Back Flow
  • Allegro PCB Editor Intermediate Techniques

Click here to view course learning maps, and here for complete course catalogs.