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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Instructor Led1.108 Sep 2014 - 12 Sep 2014Cadence San Jose > ES Training Room SJ1140  Hrs3500.00Register »
Instructor Led1.113 Oct 2014 - 17 Oct 2014Cadence Chelmsford > ES Training Room Groucho40  Hrs3500.00Register »
Instructor Led1.120 Oct 2014 - 24 Oct 2014Cadence San Jose > ES Training Room SJ1140  Hrs3500.00Register »

Course ID:  ES_84497_1.1

"Great overview of UVM. Instructor knew material very well and was very good about answering our sometimes quite out of the box questions."
Jacob Harer, Allegro MicroSystems

Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses cover advanced topics.

Universal Verification Methodology (UVM) is the Accellera standard class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments.

The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features.

The majority of the course describes a methodology for using the building blocks of the UVM class library to create configurable, reusable UVM Verification Components (UVCs) based on a standard architecture, and with embedded randomization, coverage, and self-checking. The course then shows you how to combine multiple UVCs into a flexible, powerful verification environment.

Learning Objectives

After completing this course, you will be able to:

  • Understand the features and capabilities of the UVM class library for SystemVerilog
  • Create and configure UVCs for your verification environments
  • Combine UVCs to implement a verification environment based on a proven methodology for creating reusable, scalable, and robust verification components

Software Used in This Course

  • Incisive Enterprise Simulator XL

Software Release(s)

  • Incisive 12.2

Course Agenda

Day 1

Essential SystemVerilog and object-oriented design:

  • Review of basic SystemVerilog classes
  • Polymorphism and casting
  • Virtual classes and methods
  • Developing robust class methods
  • Class-based component hierarchy
  • Factory and builder design patterns

Day 2

Data, phases and simple environments:

  • Introduction to UVM methodology and universal verification component (UVC) structure
  • Overview of the design under test (DUT) and the project
  • Stimulus modeling
    • Declaring data items
    • Field automation
    • Data operations (copy, clone, print, etc.)
  • Simulation phases
    • Standard phases
    • Run-time phases
  • Creating a simple environment
    • UVM component classes
    • Structure of a simple environment
    • Messaging
    • Packaging and directory structures
  • Test classes
    • Test selection

Day 3

Configuration, sequences, and connections:

  • Controlling environment behavior
    • Configuring topology with set_config
    • Configuration database (uvm_config_db)
    • Recommendations for set_config and uvm_config_db usage
    • Factories
    • Type and instance overrides
  • UVM sequences
    • Sequence components
    • uvm_do macros
    • Alternatives to uvm_do macros
    • Nested sequences and sequence properties
    • Objection mechanism for stopping simulation
    • Sequence selection
  • Connecting to a design under test (DUT)
    • The testbench layer
    • Virtual SystemVerilog interfaces
    • Assigning interfaces using the configuration database

Day 4

Multi-channel sequences and scoreboards:

  • Interface and module UVCs
    • Integrating multiple UVCs
    • UVCs with multiple agents
  • Multi-channel sequences (virtual sequences)
    • Virtual sequencers
    • Defining virtual sequences
  • Building a scoreboard
    • Scoreboard requirements and considerations
    • Connecting components with TLM analysis interfaces

Day 5

Transaction-level modeling (TLM) and coverage

  • Transaction-level modeling (TLM)
    • Concepts and terminology
    • Simple uni-directional connections (put, get, peek)
    • More complex connections (transport, analysis)
    • TLM fifo connections
    • Hierarchical connections with export
  • Functional coverage modeling
    • Coverage-driven verification overview
    • Coverage considerations in a UVC

Lab Exercises

Lab exercises are structured around the verification of a real-life router design.

  • Creating simple stimuli
  • Universal Verification Component (UVC) architecture
  • Factories and configuration control
  • Sequences
  • Integrating multiple UVCs
  • Writing multichannel and system-level tests
  • Building a scoreboard
  • TLM connections
  • Functional coverage


  • Design engineers
  • Verification engineers


You must have:

  • Experience with SystemVerilog

In particular, it would be advantageous to review the following topics before attending the class:

  • Declaring and using class instances, including static members
  • Class inheritance and aggregation (composite classes)
  • Class property randomization
  • Randomization constraints—relational, distribution, and conditional
  • Subprograms, including void functions

Related Courses

  • SystemVerilog Language and Application
  • SystemVerilog for Design
  • SystemVerilog for Verification

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