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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online Subscription Available 24 hours, 7 days a week.Online2912.00Register »
Online1.1Available 24 hours, 7 days a week.Online  2730.00Register »
Instructor Led1.225 Jul 2016 - 29 Jul 2016Cadence San Jose > ES Training Room SJ1140  Hrs3640.00Register »
Instructor Led1.226 Sep 2016 - 30 Sep 2016Cadence Chelmsford > ES Training Room Groucho40  Hrs3640.00Register »

Course ID:  ES_84497_1.2

"Labs are the best training material. Doing the labs helped me a lot to understand the covered material during the course."
Ivan Santos, Texas Instruments

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Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses cover advanced topics.

Universal Verification Methodology (UVM) is the Accellera standard class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments.

The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features.

The majority of the course describes a methodology for using the building blocks of the UVM class library to create configurable, reusable UVM Verification Components (UVCs) based on a standard architecture, and with embedded randomization, coverage, and self-checking. The course then shows you how to combine multiple UVCs into a flexible, powerful verification environment.

Learning Objectives

After completing this course, you will be able to:

  • Understand the features and capabilities of the UVM class library for SystemVerilog
  • Create and configure UVCs for your verification environments
  • Combine UVCs to implement a verification environment based on a proven methodology for creating reusable, scalable, and robust verification components

Software Used in This Course

  • Incisive Enterprise Simulator XL

Software Release(s)

  • Incisive 14.1

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1 - Section 1: Essential SystemVerilog and Object-Oriented Design for UVM

  • Review of basic SystemVerilog classes
  • Polymorphism and casting
  • Virtual classes and methods
  • Developing robust class methods
  • Class-based component hierarchy
  • Factory and builder design patterns

Days 2-4 – Section 2: UVM Verification Environment

Data, phases, and simple environments:

  • Introduction to UVM methodology and Universal Verification Component (UVC) structure
  • Overview of the router lab project
  • Stimulus modeling
    • Declaring data items
    • Field automation
    • Data operations (copy, clone, print, and so on)
  • Simulation phases
    • Standard phases
    • Run-time phases
  • Creating a simple environment
    • UVM component classes
    • Structure of a simple environment
    • Messaging
    • Packaging and directory structures
  • Test classes
    • Test selection
  • Configuration
    • Configuring topology with the configuration database (uvm_config_db)
    • How configuration works, with rules, examples and debugging
    • set_config method calls (deprecated in UVM1.2)
  • Type Overrides and the Factory
    • Constraint layers and behavior modification
    • Factories
    • Type and instance overrides
  • UVM sequences
    • Sequence components
    • uvm_do macros
    • Alternatives to uvm_do macros
    • Nested sequences and sequence properties
    • Objection mechanism for stopping simulation
    • Objection changes in UVM1.2
    • Sequence selection
  • Connecting to a DUT
    • The testbench layer
    • Virtual SystemVerilog interfaces
    • Assigning interfaces using the configuration database
  • Interface and module UVCs
    • Integrating multiple UVCs
    • UVCs with multiple agents
    • Configuration objects
  • Multichannel sequences (virtual sequences)
    • Virtual sequencers
    • Defining virtual sequences
  • Building a scoreboard
    • Scoreboard requirements and considerations
    • Connecting components with TLM analysis interfaces

Day 5 – Section 3: Further UVM

  • Transaction-level modeling (TLM)
    • Concepts and terminology
    • Simple, unidirectional connections (put, get, peek)
    • More complex connections (transport, analysis)
    • TLM FIFO connections
    • Hierarchical connections with export
    • TLM2
  • Functional coverage modeling
    • Coverage-driven verification overview
    • Coverage considerations in a UVC
  • Introduction to register modeling
    • Overview of the purpose and structure of register modeling
    • Generation of a register model
    • Integration into an environment
    • Simulation using built-in and user-defined register sequences
  • Conclusions
  • Appendix: Sequence Library


  • Design engineers
  • Verification engineers


You must have:

  • Experience with SystemVerilog

In particular, it would be advantageous to review the following topics before attending the class:

  • Declaring and using class instances, including static members
  • Class inheritance and aggregation (composite classes)
  • Class property randomization
  • Randomization constraints—relational, distribution, and conditional
  • Subprograms, including void functions

In addition, some knowledge of object-oriented design is advantageous but not essential. No prior knowledge of UVM is required.

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