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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online Subscription Available 24 hours, 7 days a week.Online2800.00Register »
OnlineIC6.1.3Available 24 hours, 7 days a week.Online  788.00Register »
Instructor LedIC6.1.6Scheduled upon demand 8  Hrs1050.00Express Interest »
Instructor LedIC6.1.5Scheduled upon demand 8  Hrs1050.00Express Interest »
Virtual InstructorIC6.1.3Scheduled upon demand 8  Hrs1050.00Express Interest »

Course ID:  ES_84466_IC6.1.6

Course Description

This is an Engineer Explorer course. In some labs, you are expected to use the Virtuoso® Floorplanner without assistance to solve loosely defined problems. You need to be familiar with top-level floorplanning and Virtuoso XL connectivity-driven layout.

When you finish this course, you will be able to create a top-level floorplan. In this course, you use the floorplanner to calculate the area required for the top-level boundary and the top-level blocks. You create the I/O rows, place the I/O pads, insert the filler cells, place the corner cells, generate and place the top-level blocks. Some of the blocks are existing blocks and some are calculated for their area. You also create a top-level floorplan without using an existing layout so you can see how to calculate the area and then modify the blocks to fit in a specific top-level boundary.

Learning Objectives

After completing this course, you will be able to:

  • Generate an abstract from an existing layout
  • Generate soft blocks to represent a layout that has not been created yet
  • Specify which cells to use when generating the blocks in the hierarchy
  • Place the blocks in the top level
  • Optimize the pin placements for top-level routing
  • Edit the soft-block shapes to accommodate the available area and pin alignments
  • Use soft blocks for all the top-level blocks to allow for maximum flexibility in your floorplan
  • Use the SKILL® API-Based Flow for Virtuoso Floorplanner

Software Used in This Course

  • Virtuoso Layout Suite GXL

Software Release(s)

  • IC 6.1.6

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

  • Online help system (cdnshelp)
  • Floorplanner overview
  • Creating an abstract
  • Technology file
  • Floorplanning strategies
  • Setting constraints
  • Configuring the physical hierarchy
  • Using hard and soft blocks
  • Setting soft-block parameters to calculate area
  • Generating the physical hierarchy blocks
  • Creating I/O Rows
  • Placing I/O Pads
  • Inserting Filler Cells
  • Placing Corner Cells
  • Placing blocks
  • Analog/Mixed
  • Setting constraints
  • Editing the top-level blocks
  • Optimizing pins
  • Creating a top-level floorplan with all soft blocks
  • Using the SKILL API Based Flow to generate physical hierarchy

Audience

  • IC Designers
  • Analog/Mixed-Signal IC Designers
  • Analog IC Designers
  • Custom Circuit Designers
  • Chip Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Cadence® physical design tools
  • Layout design experience
  • Virtuoso XL connectivity-driven layout
  • Top-level floorplanning

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