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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Instructor Led12.2Scheduled upon demand 32  Hrs2800.00Express Interest »

Course ID:  ES_82133_12.2

Course Description

This is an Engineer Explorer course that covers advanced topics that are not suitable for beginners. The course is the next level after the Specman® for Block-level Environment Developers course. This course covers the more advanced e language and Incisive® Specman tool features.

The advanced e language and Specman features are described in the wider context of scaling and reusing verification environments from the block-level through large system-level environments. These environments are typically constructed from many different languages, such as e, SystemVerilog, and SystemC. This course follows and describes the recommendations of the Cadence® UVM e methodology. This course provides essential hands-on experience, with a combination of lecture and labs.

This course covers a variety of advanced topics including:

  • Advanced functional coverage
  • Module-to-system reuse
  • Macros
  • Reflection API for the e language
  • Advanced debugging features
  • Advanced sequences
  • Register and memory modeling
  • Optimizing regression times using the Specman Advanced Option (SAO)

Learning Objectives

After completing this course you will be able to:

  • Scale verification environments from a block to the system level
  • Maximize reuse of your verification environments
  • Implement and interface to reference models in other languages
  • Implement and manipulate virtual and layered sequences
  • Advanced sequence use models using the UVM-e sequence API
  • Extend the e language with macros
  • Optimize for performance and productivity

Software Used in This Course

  • Incisive Enterprise Simulator

Software Release(s)

  • INCISIV 12.2

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Cadence metric driven verification (MDV) methodology overview
  • Verification process overview
  • Multilanguage UVM (UVM e)
  • Reference models
  • Interfacing to other languages
  • e template types
  • UVM e TLM connections
  • Advanced coverage implementation

Day 2

  • Module-to-system reuse
  • Reflection facility
  • Extending the e language using macros

Day 3

  • Efficient use models for the Specman tool (optimizing performance and productivity with SAO)
  • Advanced temporal expressions
  • Advanced messaging: structured debug messages (SDMs)

Day 4

  • Debugging in the Specman environment (Specman SimVision interface)
  • Debugging using the Incisive Debug Analyzer (IDA)
  • Advanced use of UVM e sequences (sequence driver API)
  • Register and memory modeling introduction (vr_ad)

Audience

  • Current Specman module-level testbench designers who want to
    • Learn advanced e language features
    • Create system-level testbenches efficiently

Prerequisites

You must have:

  • Practical experience with the e language, Specman, and UVM-e compliant verification environments.

Or you must have completed this course:

  • Specman Fundamentals for Block-level Environment Developers

Related Courses

  • Verification Planning using Enterprise Planner

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