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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Instructor Led15.1Scheduled upon demand 32  Hrs2912.00Express Interest »

Course ID:  ES_82133_15.1

Course Description

This is an Engineer Explorer course which covers advanced topics that are not suitable for beginners. The course is the next level after the Specman® for Block-level Environment Developers course. This course covers the more advanced e language and Incisive® Specman tool features.

The advanced e language and Specman features are described in the wider context of scaling and reusing verification environments from the block-level through large system-level environments. These environments are typically constructed from many different languages, such as e, SystemVerilog, and SystemC. This course follows and describes the recommendations of the Cadence® UVM e methodology. This course provides essential hands-on experience, with a 50/50 combination of lecture and labs.

This course covers a variety of advanced topics including:

  • Comprehensive functional coverage
  • Module-to-system reuse
  • Macros
  • Automated checking concepts and features
  • UVM Multi-language Open Architecture library
  • Reflection API for the e language
  • Specman Memory Analysis
  • Advanced sequences
  • Register and memory modeling
  • Optimizing regression times using the Specman Advanced Option (SAO)

Learning Objectives

After completing this course, you will be able to:

  • Scale verification environments from a block to the system level
  • Maximize reuse of your verification environments
  • Use the UVM Multi-language Open Architecture library to achieve multi-language communication, synchronization and configuration
  • Implement and manipulate virtual and layered sequences
  • Implement Advanced sequence use models using the UVM-e sequence API
  • Extend the e language with macros
  • Utilise the powerful combination of Reflection and Macros
  • Optimize for performance and productivity
  • Implement an instance based coverage model and using a combination of procedural code and coverage
  • Model registers and memories effectively using the vr_ad package

Software Used in This Course

  • Incisive Enterprise Simulator

Software Release(s)

  • INCISIVE 15.1

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Reference models
  • Interfacing to other languages with UVM e TLM connections
  • Defining and extendingetemplate types
  • Comprehensive Instance Based Functional Coverage.
  • Specman Memory Analysis – Understanding how Specman uses memory and how to optimally configure that

Day 2

  • Reflection facility – Introspection in the e language and its application
  • Efficient use models for the Specman tool (optimizing performance and productivity with SAO)
  • Using e libraries - elibs
  • Extending the e language using macros including use of Reflection

Day 3

  • Module-to-system reuse
  • Advanced use of UVM e sequences (sequence driver API)

Day 4

  • UVM-ML Open Architecture Library - multi-language communication, synchronization and configuration
  • Register and memory modeling introduction (vr_ad)
  • Advanced temporal expressions


  • Current Specman module-level testbench designers who want to


    • Learn advanced e language features
    • Create system-level testbenches efficiently


Practical experience with the e language, Specman, and UVM-e compliant verification environments or you must have completed the following courses:

Related Courses

Specman Fundamentals for Block-Level Environment Developers

Metric Driven Verification using Incisive vManager

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