Part of the Cadence®
acceleration and emulation technologies, transaction-based acceleration (TBA) 2.0 helps design and verification teams reduce their verification time by providing new infrastructure and guidelines to support a reusable accelerated verification environment. With TBA 2.0, teams benefit from a 100x–10,000x increase in performance over RTL simulation, even more on designs of 2M gates or larger. They also benefit from a direct transaction-based interface to the desired testbench language and a highly productive simulator-like environment. TBA 2.0 is compliant (and can combine VIP) with both the Accellera SCE-MI 1.1 and SCE-MI 2.0 draft standards. The result of many key Cadence technology enhancements, TBA 2.0 is unique in its ability to boost productivity for customers.
TBA 2.0 is fully supported by the Incisive Enterprise Simulator and the Palladium® series of accelerators/emulators. This TBA 2.0 capability also includes features that simplify the creation and debugging of transaction-based test environments, such as transaction-level model (TLM) direct interface and native hardware verification language (HVL) adaptors. These capabilities make the HDL side code unaware of the HVL language used and improve ease-of-use and reusability. The same TLMs used for system-level design and as reference models for RTL development can be used in conjunction with RTL acceleration.
Central to TBA 2.0’s effectiveness is the Incisive simulator unique congruency feature, which ensures the same results in simulation and acceleration without needing to change any design or testbench models. This results in much faster debug and an overall reduction in verification time.
TBA 2.0 also supports the DirectC feature, allowing users to verify their design without a simulator connected at runtime. This capability targets users who would like to incorporate C/C++ testbenches (or software object libraries) connected directly to their emulation environment. DirectC supports both master and slave modes to further increase flexibility during the verification process. The DirectC feature is 100% SCE-MI 2.0 draft standard-compliant with support for macro, SV DPI ,and Pipes modes.
Benefits of TBA 2.0
- Superior debug capabilities allow transaction-based source-level debug, viewing of transactions and signals within the same window, and automatic transaction recording
- FullVision and InfiniTrace capabilities allow access to all design components and signals throughout the whole runtime session
- Delivers performance approaching emulation speed (1MHz+)
- Multi-language native HVL and C/C++ transaction-based adaptors ensure easy migration from the simulation environment (with the user’s desired testbench language), easy debug, and easy creation of VIP models
- DirectC allows C/C++ testbenches and/or compiled software libraries to be connected directly to the emulator (without any simulation environment) with support for standard interfaces (SCE-MI, SV-DPI)
- Simulation-like environment with full congruency ensures fast “learning curve” and debug for simulation customers
- Constraint and pseudo randomization enable advanced verification capabilities
- Delivers a full methodology including scripts, examples, and detailed documents
- Ability to mix signal-based and transaction-based acceleration enables fast and incremental bring-up of design and verification environments much earlier in the design process
- Multiple synchronization modes provide more flexibility
- Hybrid mode enables a combination of TBA and in-circuit emulation in a single configuration and allows customers to migrate from one mode to another
- Automatic variable length messaging reduces testbench creation time and optimizes testbench efficiency
- TBA performance profiler highlights any performance bottlenecks and points users to where they need to modify their testbench to achieve the best results
- Direct OSCI® TLM 2.0 connection enables direct connection to a design
written in a high-level of abstraction
- SCE-MI 2.0 (and SCE-MI 1.1) standard compliant capability enables customers to plug in third-party VIP
The Incisive TBA methodology supports the Incisive verification IP (VIP) library of specific protocols such as PCI Express, Ethernet, AHB, and AXI. The Incisive VIP library delivers fast RTL simulation and a high-speed accelerated hardware mode with a single transactor for both environments. These same transactors support a high-speed simulation interface for architectural modeling at the transaction level or for high-level software development.