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Home > Tools > System Design and Verification > Memory Model Portfolio (MMP) for Palladium Series

Memory Model Portfolio (MMP) for Palladium Series 

An off-the-shelf plug-and-play library, the Cadence® Memory Model Portfolio provides a pre-validated system-level emulation solution with memory device models for the Cadence Palladium® series. The memory device models in the Memory Model Portfolio enable rapid deployment of high-performance system-level emulation by providing an extensive array of high-quality synthesizable models for industry-standard memory devices that are widely used in networking, storage, wireless, and multimedia applications. Benefits:
  • Simplifies and speeds verification deployment
  • Enables verification IP reuse
  • Delivers highest performance with the least abstraction
  • Reduces system risk in verifying designs quickly and efficiently
  • Provides flexible use models for simulation acceleration, synthesizable testbench, and in-circuit emulation
Enhance Validation Productivity
With the Memory Model Portfolio, you can improve your team’s validation productivity by taking advantage of complex state-of-the-art memory and storage protocols without tying up engineering resources. The portfolio combined with the Palladium series can help you and your team quickly construct a complete emulation environment that applies real-world system operating conditions to your design.

The extensive portfolio includes models across major device families and vendors. The models are fully synthesizable with minimal gate capacity usage. For fast completion, time-intensive functions are internally clocked and optimized.

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