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Accelerated Verification IP 

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AVIP: A Necessity for Verifying Today’s SoCs and Subsystems
Verification teams commonly find that the large scale of their designs exceeds the ability of simulation to effectively verify their designs. This is clearly the case at the system-on-chip (SoC) level and increasingly true at the subsystem level.

To help you verify such large designs, Cadence provides our Palladium® XP Verification Computing Platform in conjunction with high-performance Accelerated Verification IP (AVIP). By facilitating the high-speed transfer of interface traffic through a design under test in Palladium XP, Cadence® AVIP allows engineering teams to dramatically boost the verification performance of designs at any integration level: intellectual property (IP), subsystem, SoC, and system. With our off-the-shelf solution, verification teams can focus on finding bugs instead of developing infrastructure.

Cadence AVIP Ensures High Performance
To deliver high-end verification and validation performance, Cadence AVIP takes full advantage of the Palladium XP architecture, allowing you to achieve speeds that are hundreds to thousands of times greater than with simulation. AVIP is architected to minimize the time spent on the accelerator through an optimized core. And since you must perform a variety of verification applications during the life of the project, Cadence AVIP provides a selection of user interfaces, each of which is optimized for the specific task.

Cadence AVIP also provides the ability to control the trade-off between performance and verification functionality (such as checking and coverage). This control is essential because tradeoffs evolve as the design progresses from IP/block-level to SoC or system-level validation.

Cadence AVIP provides “knobs” to control verification functionality vs. performance tradeoff


Support for Multiple Protocols and User Interfaces
To ensure that each user’s specific requirements are met, Cadence supplies AVIP for the most commonly needed protocols.

Cadence AVIP protocol availability


In addition, each AVIP supports several user interfaces to enable a variety of verification applications. These include hardware verification, data-flow validation, software development, and more.

Based on Proven Simulated VIP
Cadence has leveraged our leadership in simulated verification IP (VIP) and extended our VIP Catalog to also support high-performance acceleration. This is achieved through the unique architecture of the AVIP that decouples the testbench interface from the acceleration-optimized core.

You'll not only benefit from the maturity of the VIP cores, but also from a consistent test writing UI—the PureSpec User Interface acquired from Denali—that is applicable whether the VIP is used for simulation, acceleration, or both.

With Cadence AVIP, you can easily reuse your simulated UVM testbenches. Employing only a single testbench saves effort, as you move from block-level to system-level validation. And, of course, the testbench can be eliminated when and if needed to maximize performance for SoC/system validation and/or software development.

Key Cadence AVIP Benefits
  • Ensures high performance
  • Allows you to easily control performance vs. verification capability tradeoff
  • Enables testbench reuse; provides the same results for simulation and acceleration
  • Provides a consistent user interface for efficient test writing
 
 

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