Cadence® Incisive® System-Level Verification IP (VIP) includes the following groups of accelerated VIP models:
- Transaction-based acceleration (TBA) VIP provides off-the shelf transactors for protocols driven by SystemC® or e testbenches with Incisive simulation acceleration products (Xtreme® and Palladium® series).
- Assertion-based acceleration (ABA) VIP provides protocol monitors that can be incorporated into Incisive acceleration/emulation environments with Xtreme and Palladium systems.
Incisive Transaction-Based Acceleration Verification IP
Incisive TBA VIP is built with acceleratable bus functional models (BFMs) to enable true transaction-based acceleration. Incisive TBA VIP allows the simulator and accelerator to communicate exclusively through transactions to lower testbench modeling overhead and increase acceleration speeds.
Transaction-based verification allows the development of simulation testbenches and debug/analysis of simulation results at a higher level of abstraction over using HDL. A transaction-based verification methodology uses transactions (high-level transfer of data from one device to another over a well-defined interface) and transactors (devices that execute transactions). A transactor connects to a design under verification at the design interface and serves as an abstraction layer between the test program and the design. Each transactor is composed of an HDL-synthesized BFM and a hardware verification language (HVL) proxy model communicating over TBA interfaces. The BFM is written in synthesizable SystemVerilog RTL and the proxy model is written in C, C++, SystemC, and
e.
Incisive TBA VIP delivers fast RTL simulation and a high-speed accelerated hardware mode using common transactors for simulation and acceleration. These transactors can be used for mixed RTL/transaction-level model (TLM) architectural verification or for mixed hardware/high-level software development.
Benefits of Incisive TBA VIP
- Provides an easy-to-configure SystemC TLM interface
- Offers a complete master/slave protocol solution
- Provides identical results for both simulation and acceleration
- Speeds up the verification effort
- Reduces the testbench development effort
- Catches hardware protocol bugs during simulation and acceleration
- Checks can be individually enabled/disabled
- Can communicate functional coverage data
- Supports a full suite of common protocols and verification environments
- 10 Gigabit Ethernet (TBA 2.0)
- PCI Express 2.0 (TBA 2.0)
Incisive Assertion-Based Acceleration Verification IP
Incisive ABA VIP enables the use of assertions for verifying designs using high-performance Palladium or Xtreme accelerators/emulators. Incisive ABA VIP is particularly useful for monitoring bus protocols and is well-suited for verifying interfaces such as switches or bridges. The assertions are written in PSL, SystemVerilog, and OVL, and using the Incisive Assertion Library.
Incisive ABA VIP provides compliance checks together with cover checks, allowing design and verification teams to explore interesting protocol scenarios efficiently. It maximizes quality, predictability, and productivity while minimizing protocol expertise needed and verification environment bring-up time.
Incisive ABA VIP can be used for a variety of applications including debug of missing constraints, rapid sanity checks, and compliance verification. It uses assertion-based verification (ABV) techniques to identify bugs during simulation and acceleration. Incisive ABA VIP also allows users to easily leverage the power of ABV plus acceleration to run a comprehensive suite of tests and speed verification closure.
Benefits of Incisive ABA VIP
- Offers a complete master/slave protocol monitor solution
- Catches protocol hardware bugs during simulation and acceleration
- Checks can be individually enabled/disabled
- Supports HDL-only mode of operation, requiring no SystemC compilation
- Assertions provide functional coverage
- Supports AMBA AHB, AMBA AXII, Ethernet (MII, GMII), and USB 2.0 protocols
In addition to the Incisive accelerated VIP, Cadence also delivers the industry's broadest and deepest VIP portfolio known as Universal Verification Components (UVCs). UVCs have been proven on thousands of verification projects worldwide and support more than 30 protocols, including
PCI Express,
AMBA AHB and AXI,
Ethernet,
USB,
OCP, and
SATA. The Cadence UVCs offer a unique automated protocol Compliance Management System (CMS), compliance with the Open Verification Methodology, and feature the Cadence metric-driven verification (MDV) flow. Cadence provides the single best choice for advanced testbench verification predictability, productivity, and quality.