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Blogs

Whiteboard Wednesdays - Taking Command of MIPI PHYs - M-PHY

In this week's Whiteboard Wednesdays, the second installment of a three-party series, Kevin Yee continues his earlier discussion on "taking command" of MIPI PHYs. Here, Kevin discusses M-PHY, its architecture, and the protocol's functionality...  Read More »
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400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet Standards Meeting

Here is another report from an IEEE 802.3 Ethernet standards meeting, this time held in Norfolk, Virginia. Norfolk has a large naval base and, while I was there, I got to see the USS Cole and the Nimitz-class aircraft carriers USS Theodore Roosevelt and...  Read More »
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DDR4 in 16nm FinFET: Future-Proof Your SoC Design

Cadence this week (May 19, 2014) is announcing the first DDR4 PHY IP built on TSMC's 16nm FinFET process. The 3200Mbps DRAMs that can take best advantage of this capability aren't shipping in volume yet - but you can "future-proof" your...  Read More »
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DDR4 Roadmaps and Strategic IP Planning

New DDR4 PHY IP technology on TSMC 16nm FinFET process offers a clear path from 2400 Mbps performance to 3200 Mbps....  Read More »
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Embedded Vision Summit: Focus on Autonomy and Recognition

Some eras introduce new technologies that take electronics systems (and engineering thinking) to a different level. Such is the case with embedded vision....  Read More »
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DAC 2014: Semiconductor IP Trends Revealed at “IP Talks!”

Want to know more about the design and verification IP that makes advanced system-on-chip (SoC) design possible? There's no better place than IP Talks!, a series of ongoing presentations at the ChipEstimate.com booth (#1533) at the Design Automation...  Read More »
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Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4 technology. He also walks you through the improvements of DDR4 over DDR3, as well as the memory standard's specifications and the challenges of meeting these specifications...  Read More »
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Webinar: Addressing MCU Mixed-Signal Design Challenges

ARM-Cadence webinar offers insights into MCU mixed-signal design challenges and today's implementation and verification environments....  Read More »
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What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units. Alternate unit display requires the enablement of the user preference variable ‘showmeasure_altunits’. ‘Show Measure’...  Read More »
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High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM...  Read More »
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