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Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
By Richard Goering
on March 12, 2013
Lip-Bu Tan, Cadence president and CEO, is excited about ongoing innovation within the electronics industry - but he's also aware of challenges such as advanced node lithography, complexity, time-to-market, and rising design costs. In a keynote speech...
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Filed under: 3D-IC, ARM, CDN Live!, CDNlive, CDNLive 2013, CDNLive Silicon Valley, cloud, Cosmic Circuits, CoWoS, design costs, FinFets, Internet of Things, IP, keynote, Lip-Bu Tan, lithography, mobile Internet, mobility, Samsung, semiconductors, SoC, Tan, Tensilica, TSMC
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Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
By Axel Scherer
on March 12, 2013
Udacity/Cadence MOOCs CS 348 course on Functional Hardware Verification will go live on Mar 12, 2013....
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Filed under: Axel Scherer, Cadence, CS348, e language, Functional Verification, hardware verification, IEEE 1647, Incisive, MOOC, on-line class, on-line course, Scherer, Specman, Udacity, verification, verification course
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CDNLive Paper Preview: RTL Performance Analysis of ARM Interconnect IP
By Richard Goering
on March 11, 2013
System on chip (SoC) interconnect must meet the performance requirements of increasingly demanding, complex chips -- but traditional modeling and verification techniques don't shed much light on bandwidth and latency. A new approach to analyzing and...
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Filed under: AMBA, AMBA Designer, ARM, cache coherent interconnect, CCI, CDN Live, CDNlive, CDNLive 2013, CoreLink, Heaton, Industry Insights, interconnect, interconnect IP, Interconnect Workbench, Orme, performance analysis, RTL, Simulation, system IP, TLM, traffic models
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Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013
By Richard Goering
on March 11, 2013
If you're familiar with the popular, cutting-edge TED Talks lecture series, then I would call the Electronic Design Process Symposium ( EDPS ) the "TED Talks" of EDA. Now in its 20 th year, this IEEE-sponsored workshop brings together the...
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Filed under: 3D IC, 3D-IC, CAD methodologies, Cadence, Dan Nenni, design collaboration, EDA, EDA workshop, EDP, EDPS, EDPS 2013, Electronic Design Process, ESL, FinFET, Gary Smith, IEEE, Industry Insights, Ivo Bolsens, Monterey, system-level design, TED Talks
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DVCon 2013: Functional Verification Is EDA’s “Killer App”
By Joseph Hupcey III
on March 10, 2013
With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from...
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Filed under: apps, DVcon, DVCon 2013, e, e code, e language, formal, Formal Analysis, formal apps, Functional Verification, Joe Hupcey III, methodology, metric driven verification (MDV), metrics, papers, Richard Goering, Specman, Specman e, Team Verify, UVM e, verification
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CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
By Vasu Madabushi
on March 10, 2013
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user...
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Filed under: AppliedMicro, ARM, ARMv8, Avago, CCOpt, CDNLive, CDNLive Silicon Valley, CDNLive! Cadence, Cortex-A15, Cortex-A57, Cortex-A7, digital, Digital Implementation, EDI, Encounter Digital Implementation, GigaOpt, high performance, low power, NVidia, RC-Physical, SoC
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System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
By Frank Schirrmeister
on March 8, 2013
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December...
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Filed under: Accelerated Verification IP, Acceleration, AMD, ARM, AVIP, Bluespec, Cadence, CDNLive, CDNLive!, dynamic power analysis, embedded software, Emulation, Fast Models, Freescael, Imperas, Incisive, Intel, low power, low power optimization, Palladium XP, PXP, RPP, Samsung, Schirrmeister, System Design and Verification, System Development Suite, System to Silicon Verification, Teledyne LeCroy FPGA Based Prototyping, VCP, Verification Computing Platform, Verification IP, Virtual System Platform, VSP
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Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes
By Richard Goering
on March 6, 2013
The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence"...
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Filed under: 1801-2013, ARM, Biggs, Cadence, CPF, CPF 2.0, DVCon 2013, IEEE 1801, IEEE 1801-2013, low power, low power coalition, PIEEE1801, power formats, power intent formats, RevCom, Si2, UPF, UPF 2.1
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DVCon 2013 Expert Panel: How to Succeed with Verification Planning
By Richard Goering
on March 5, 2013
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon...
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Filed under: best practices, Brennan, Cadence, coverage, DVCon, DVCon 2013, formal verification, Functional Verification, Incisive Enterprise Manager, Industry Insights, Maxim, Metric-driven verification, Mixed-Signal, Nitzan, Oski, Paradigm Works, Sarkar, Simulation, Singhal, Sprott, Stellfox, verification plan, verification planning, verilab, vPlan, Xilinx
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JBYOB (Just Bring Your Own Browser): Interactive Labs on Udacity CS348 Functional Hardware Verification – No Installation Required
By Axel Scherer
on March 5, 2013
Interactive coding in the web browser. Preview of the interactive features of Udacity CS348 Functional Hardware Verification course....
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Filed under: Course, CS348, Functional Verification, IEEE 1647, interactive labs, MOOC, on-line, online course, Scherer, Udacity
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