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FinFETs, Advanced Process Nodes, and Parasitic Extraction

Cadence's Hitendra Divecha talks about advanced-node and FinFET design challenges and how to manage parasitic extraction....  Read More »
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Designer View – How Emulation/Virtual Prototyping “Hybrid” Speeds Software Development

200X. That's the number with which Moshe Berkovich, senior engineer at fabless semiconductor provider CSR , started a 15-minute talk that is now a recorded presentation on Cadence.com. And 200X is the performance improvement that his team was able...  Read More »
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New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog and UVM Environments

There is always a demand for learning something simply and quickly on your own in some corner of the world. The big challenge that I have faced with learning is how to find the right learning vehicle that helps me discover what I didn't already know...  Read More »
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What's in Store for the Electronics Industry in 2H 2014?

The electronics industry outlook for the second half of 2014 is looking more bullish than expected, thanks in part to the coming launch of the Apple iPhone 6....  Read More »
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Whiteboard Wednesdays - Defining Different Types of USB Controllers

In this week's Whiteboard Wednesdays, Jacek Duda takes a closer look at different types of USB controllers and their roles in today's devices....  Read More »
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Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since then, our PCIe offerings have evolved to include the lowest power PHY solutions available, FPGA platforms for prototyping, software drivers, and the industry’s...  Read More »
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Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support, 2Q 2014

Cadence Online Support, http://support.cadence.com , provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support. In the June release...  Read More »
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Archived Webinar – An Introduction to High-Level Synthesis (HLS)

High-level synthesis (HLS) is rapidly entering the IC design mainstream - but how much do you know about this emerging technology? A recently archived Cadence webinar sets the record straight about what HLS is (and is not), how it works, who's using...  Read More »
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What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6 Has It!

Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive...  Read More »
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DAC 2014 Panel: Chip, Package, and Board Design Must be Reconsidered

High-speed cross fabric interface design requires an understanding that digital is more analog and that chip, package and board design must be reconsidered, according to a DAC 2014 panel of experts....  Read More »
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