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Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP
By Jeffrey Gallagher
on April 11, 2013
The level of ease and efficiency you experience in selecting the items needed for modifying in your substrate can mean the difference between a great design experience and an exercise in frustration and futility. With the 16.6 release, Cadence IC Packaging...
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Filed under: 16.6, Allegro Package Designer, APD, APD 16.6, Digital SiP desgn, Digital SiP design, IC Package, IC Package Physical layout and co-design, IC packaging, IC Packaging & SiP design, IC packaging documentation, package, packaging, SiP, SiP Layout, wirebonding, wirebonds
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What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6!
By Gerald "Jerry" Grzenia
on April 9, 2013
Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer...
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Filed under: "PCB design", 16.6, Allegro 16.6, Allegro GUI, Allegro PCB Editor, constraint databases, constraint difference, Constraint Manager, Constraint-driven PCB Design flow, constraints, design, ECSets, electrical constraints, Grzenia, layout, PCB, PCB design, PCB Editor, PCB Layout and routing, SPB
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Videos, Presentations Highlight Front-End IC Design Methodologies
By Richard Goering
on April 9, 2013
Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations...
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Filed under: ARM, Conformal ECO, DFT, ECOs, Encounter, Encounter Test, equivalence checking, FED, FED Technology Summit, front end design, front end design summit, front-end, Logic Design, logic synthesis, physical aware synthesis, RC, RTL Compiler, RTL synthesis, synthesis, test coverage
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Develop for Debugability – Part 1
By Team Specman
on April 8, 2013
Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience...
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Filed under: AF, aspect-oriented programming, Daniel Bayer, debug, debugability, debugging, e language, encapsulate, encapsulating aspects, Functional Verification, Incisive Enterprise Simulator (IES), simulation, Specman, verification
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CDNLive Silicon Valley 2013 Proceedings Available for Download!
By Richard Goering
on April 4, 2013
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations...
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Filed under: 3D-IC, advanced node, CDN Live, CDNlive, CDNLive 2013, CDNLive papers, CDNLive presentations, CDNLive proceedings, CDNLive Silicon Valley, Custom IC, front end design, high performance, IC packaging, Industry Insights, IP, Lip-Bu Tan, low power, Martin Lund, mixed signal, PCB, signoff, system, verification, Young Sohn
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What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!
By Gerald "Jerry" Grzenia
on April 3, 2013
The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements: Grouping in Design Entry HDL (DEHDL) Allegro PCB Editor Enhancements Read on for more...
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Filed under: 16.6, Allegro 16.6, Allegro PCB Editor, Allegro RF SiP, autoplace, Cadence Design Systems, design, Design Entry, Design Entry HDL, Grzenia, PCB, PCB design, PCB Editor, PCB Layout and routing, placement edit, RF, RF PCB, Schematic, SPB
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How Hardware/Software Co-Development Fuels “Product Creation”
By Richard Goering
on April 3, 2013
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements...
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Filed under: AMBA Designer, ARM, CDNlive, Co-Design, co-verification, design authoring, embedded software, hardware/software, hardware/software co-development, Incisive, Industry Insights, IP, middleware, operating systems, OS, Palladium XP, product creation, Rapid Prototyping Platform, Schirrmeister, SoC, software/hardware, System Development Suite, Tensilica, Virtual System Platform
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Multi-Level Physical Hierarchical Flow – A New Approach for Giga-Scale ASIC Design
By Richard Goering
on April 1, 2013
A presentation at the DesignCon 2013 conference illustrated a new methodology that speeds timing closure for ASIC and SoC designs with hundreds of millions of gates. Called "multi-level physical hierarchy design," it overcomes many limitations...
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Filed under: ASIC design, DesignCon, EDI, Encounter, GigaScale, hierarchical design, hierarchy, IC Design, Industry Insights, multi-level hierarchy, multi-level physical hierarchy, partitioning, physical hierarchy, pin assignment, routing congestion, Singh
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Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
By Sathishkumar Balasubramanian
on March 29, 2013
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The...
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Filed under: AMS, AMS Designer, AMS Verification, analog, analog behavioral models, analog/mixed-signal, Cadence, CDNLive, CDNLive 2013, CDNLive SV 2013, EDI, mixed signal, mixed signal methodology guide, Mixed-Signal IP, mixed-signal verification, MS ToT, OpenAccess, SoCs, Tech on Tour, Virtuoso
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Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
By Richard Goering
on March 27, 2013
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital...
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Filed under: AMS, Analog, analog IP, analog/mixed-signal, best practices, digital verification, DVCon, DVCon 2013, Functional Verification, Industry Insights, Khan, Maxim, MDV, metric driven verification, mixed signal, Mixed-Signal, mixed-signal SoC, mixed-signal verification, MS-MDV, MS-SoC, Neyaz Khan, UVM, UVM-MS, verification
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