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Blogs

CDNLive 2014: Follow the Data to Optimize System Design--Chris Rowen

Cadence Fellow and Tensilica Founder Chris Rowen says that by "following the data," engineers can optimize their electronics systems designs. He spoke at Cadence's CDNLive Silicon Valley 2014 event....  Read More »
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Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging Layout Tools

To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that with...  Read More »
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DesignCon 2014 Video: Extraction and Simulation for Simultaneous Switching Noise

Cadence engineer Bradley Brim discusses a DesignCon 2014 paper he co-presented, centering on a key challenge in chip-package and board design today: simultaneous switching output (SSO) analysis....  Read More »
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Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include...  Read More »
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DVCon 2014 Video: HP Engineers Apply “Test Driven Development” to UVM-e

Test-driven development ( TDD ) and unit testing are methodologies that can greatly shorten functional verification time and increase quality. Engineers at Hewlett-Packard are currently applying these techniques with UVM- e (Universal Verification Methodology...  Read More »
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What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when a new specific video is produced for product features...  Read More »
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Embedded World 2014: Confronting IoT, Automotive, and Security Challenges in Electronics Design

Cadence Product Manager Frank Schirrmeister discusses five embedded systems design megatrends with Brian Fuller from the show floor of the 2014 Embedded World event in Nuremberg, Germany....  Read More »
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Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects...  Read More »
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Embedded World 2014: Silicon Labs Designs for the Internet of Things

Daniel Cooley of Silicon Labs talks with Cadence's Brian Fuller about new low-power EFM32 Gecko MCUs at Embedded World 2014 in Nuremberg, Germany...  Read More »
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DVCon 2014: How to Close the Verification Gap

JL Gray of Cadence and John Blyler of ChipDesign Magazine talk with Brian Fuller at DVCon 2014 about whether the industry created the systems verification gap it struggles with today. ...  Read More »
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