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Analog Design Validation: What is Your Recipe for Success?

Every analog circuit design goes through some kind of electrical validation step before release to manufacture. The depth and breadth of this testing depend on the design itself, the end application and of course that all important deadline. When it comes...  Read More »
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DRAMs: Historically, how bad is this downturn?

DRAMs: Another look at how bad it is: Last week, we (finally) published our summary and analysis of DRAM makers’ financial performance for the four quarters of 2008. It was the worst DRAM year ever, and remains equally dire so far into 2009. In 2008,...  Read More »
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Don't Let Power Kill Your Project

By Diego Hammerschlag Sr. Technical Leader Team FED Power has gone from an imminent threat to the cause of multiple projects across several vendors going under. I have heard of multiple projects that had working RTL prototypes and were far into the backend...  Read More »
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Why The Reports of EDA's Demise Are Greatly Exaggerated - Part 1

For about the first 15 years of my reporting on EDA, which began in 1985, EDA was a dynamic, thriving industry with double-digit annual growth rates and lots of excitement. The last few years have been different. Now the industry press and the blogosphere...  Read More »
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Industry Insights Blog Aims for Broad Perspectives

Welcome to the new Industry Insights site of the Cadence Community ! In this site, we’ll explore issues and technologies of interest to IC and systems designers and design managers from an industry-wide perspective. This blog will offer timely commentary...  Read More »
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Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.] At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title "...  Read More »
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Virtuoso, the SATs, and The Dark Knight - Part I

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight. Well, first of all, it has only been in the past few years (so this, obviously isn’t something I’ve had to do!), but today's high school students now...  Read More »
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DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were: Security ( the focus of Part 2 of this series ) EDA applications that can clearly benefit from...  Read More »
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Automated Digital Block Implementation Using Virtuoso

Have you ever found yourself laying out a digital block in Virtuoso where you have so many standard cells to place and route that you wish you could use an automated tool to place and route those cells? Maybe you even at one point considered using a Big...  Read More »
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Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm...  Read More »
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