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Tech Tip: Weighting Generation of "Extreme" Values

[ Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation Technology R&D group] Consider the case where you have a generatable variable "x" taking random values from [0..99], i.e. all values are declared equal from...  Read More »
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Heads-up: DVClub Boston Coming Up On June 1

Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great talk at DVClub entitled "Is it time to declare verification war?" . Brian had some interesting insights as usual, prompting me to start to write a blog post...  Read More »
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Memory Company Financials, 1Q09

1Q09 Better than 4Q08, but still terrible: Memory makers continued to suffer horrendous losses in 1Q09, effectively wrapping about $1.75 around each of the 4B or so units of DRAM, NOR and NAND that they shipped to end customers during the quarter. According...  Read More »
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SystemC Interoperability - Are We There Yet?

The biggest challenge in system-level design is modeling, and getting SystemC models to work together in simulation environments has been a long, hard struggle. Finally, it appears that the stars are aligned and we are converging on the three things we...  Read More »
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Things You Didn't Know About Virtuoso: Tabs and Bookmarks

Do you remember the first time you used a browser with tabs? All of a sudden, there you were...surfing two, three, four websites at once in the same window. Yee-haw! Life is good. Well, now you can do the same thing in Virtuoso. Okay, so you can't...  Read More »
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Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual...  Read More »
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Innovative Approach to Optimized FPGA Pin Assignment

Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design. The FPGA-PCB co-design solution includes proven technology from Taray Inc for...  Read More »
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ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time again for one of the most popular CDNLive! tour stops here in EMEA. The location is the beautiful European city of Munich , at the Park Hilton Hotel . The hotel overlooks...  Read More »
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System D&V at CDNLive! EMEA

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were...  Read More »
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5 min Demo: e Coding With AMIQs DVT IDE

For those of you who can't make it to the CDNLive Munich Designer Expo this week, and/or as promised in the recent interview with AMIQ about their new "DVT" Integrated Development Environment , here is a 5 minute demo introducting DVT's...  Read More »
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