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45 nm Is Turning Point For Model-Based DFM

A recent decision by TSMC to require model-based design for manufacturability (DFM) checks at 45/40 nm may push DFM into more widespread use. It’s coming too late for the several dozen DFM startups that were around a few years ago, but it could...  Read More »
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Porting EDA Applications to Multicore - Part 3

It’s easier to build a multi-threaded application from the ground up than it is to go back and rewrite legacy code – but multi-threading still raises a number of tough challenges. The Cadence Space-Based Router is a case in point. Previous...  Read More »
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Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful...  Read More »
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Q&A Interview: Andreas Kuehlmann Discusses EDA Research Directions

Andreas Kuehlmann is a Cadence fellow, director of Cadence Research Laboratories in Berkeley , and also an adjunct professor at the University of California at Berkeley. In this interview, he talks about current research activities and possible future...  Read More »
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Things You Didn't Know About Virtuoso: Editing Properties

When I was growing up, my mother would usually bake a ham for Christmas dinner. She would always cut a slice off the side before putting it in the pan to cook. One day I asked her why she did this and she replied that her mother always did it that way...  Read More »
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MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways to communicate with our current and potential customers. Over the last 13 years that I have been in this profession, I have seen many methods and vehicles used by Cadence...  Read More »
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The Great Escape, Part II: How These Companies Exited the DRAM Business

Case Histories of Significant DRAM Market Withdrawals : This article continues our earlier discussion about the same topic from last week, entitled "...Part I." It includes highlights of the most significant departures from the DRAM business over the...  Read More »
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Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all a peak at what goes on inside of Cadence. Specifically, last Thursday May 21 here at the Cadence San Jose campus we had a welcome break in our daily routines for a good cause...  Read More »
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Where's the Bridge to Cross the Great Divide?

At this year's Embedded System Conference in San Jose there was a panel with the title Who's Taking over Whom - Is EDA Moving into Embedded or Embedded into EDA? One of the analogies Mike McNamara from Cadence used was hardware and software engineers...  Read More »
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Low Power Guide from Industry Leaders

By Kenneth Chang, Core Comp AE, Frontend Solutions. Low power concerns continue to drive companies' needs for optimized ASIC methodologies, which is why one of the Si2 key initiatives continues to be the standardization of Low Power Intent. Below...  Read More »
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