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Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following me: Before discoursing on this unusually public display of affection, allow me to take a step back and announce that I've started to tweet on Twitter . While...  Read More »
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Protecting Your IP – Two Ways To Send Pirates Packing

EDA software, embedded software, and physical chips can all fall victim to piracy and misuse. How can this be prevented? Cadence architect Scott Baeder, chair of the EDA Consortium Anti-Piracy Committee, is organizing a July 28 panel at the Design Automation...  Read More »
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The Golden Age of Electronics

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota. We wanted to visit the museum for some time, but never made quite it. We even went there once last year only to find out it is closed every Monday. The history of the museum...  Read More »
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Using Constraints to Pass Configuration Options in the Unit Hierarchy (Top-Down approach)

To allow for increased solvability, some constraints that were previously uni-directional with the old “Pgen” generator are now treated by IntelliGen in a bi-directional manner by default. This behavior dramatically improves solvability and...  Read More »
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Optimization Environment Enables Effective Reuse of Existing Design Modules

In order to complete a brand new design on time, it is an important factor to effectively reuse existing design modules. The use of an automatic optimization quickly and easily increases design reuse efficiency. The following figures are examples of a...  Read More »
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Q&A Interview: Chi-Ping Hsu Describes 5 Cadence Initiatives

Chi-Ping Hsu is senior vice president of research and development for the Cadence Implementation Products Group. He is responsible for analog design and verification, digital implementation and signoff, mixed-signal design and implementation, physical...  Read More »
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Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009). In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts...  Read More »
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What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting the new FPGA System Planner (FSP) product from the Cadence Silicon Package Board (SPB) division at the recent CDNLive! EMEA event. You can watch Hemant from the...  Read More »
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Survey Shows Reasons For Internal EDA Tool Use

Internal EDA tools can fill some important gaps in the hardware design ecosystem, according to a recent email survey sent to members of the Cadence Community . In the survey, 256 respondents first indicated whether or not they use internal CAD tools....  Read More »
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Things You Didn't Know About Virtuoso: RMB, OMG! ;-)

I apologize for the Internet slang in the title ( urbandictionary calls OMG "the most irritating piece of chatroom vernacular in existence"), but I couldn't resist. Ever since IC6.1 came out, it seems like every other question gets answered...  Read More »
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