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Rethinking SSDs?

NAND Flash's SSD Vision: Wholesale replacement of HDDs by SSDs in the huge market for PCs and laptops archival storage has gleamed in the eyes of NAND Flash makers ever since Apple kicked the microHDD out of the iPod Mini and made it a SSD/Flash based...  Read More »
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FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today. Such a simple concept – I’m in a known state and I will either remain here or move to a new...  Read More »
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Q&A Interview: Charlie Giorgetti Outlines Cadence Product Solutions

Charlie Giorgetti is corporate vice president of solutions and product marketing at Cadence. In this interview, he discusses Cadence’s product strategy, and outlines five “solutions” that are the current focus of Cadence’s marketing...  Read More »
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Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and EDI System

I'm looking forward to heading out to San Francisco next week for the 46th Design Automation Conference . For my money, it's hard to beat San Francisco as a location for a trade show. Cable cars, Fisherman's Wharf, Alcatraz, San Francisco...  Read More »
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DAC '09 for the Specmaniac

The following are the "must see" items for Specmaniacs lucky enough to get travel authorization for DAC 2009 (and/or who scored a cheap ticket on Priceline.com for a spur of the moment "vacation" to scenic San Francisco). 1 - Specman...  Read More »
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What's Good About Allegro's Placement Application Mode? - Look to SPB16.2 and See!

In prior releases, Allegro PCB Editor does not provide the user the ability to place or make placement changes easily. New functionality to provide greater usability for component placement, alignment, replication of circuitry would greatly impact the...  Read More »
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At DAC Next Week

Yours truly will be at the big show next week, and I hope that all of you in the blogosphere will be able to sweet talk your management into letting you go as well. For those of you who have already won a golden ticket: * By all means let's meet in...  Read More »
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Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency...  Read More »
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Freescale Technologist Eyes Move To SystemC And TLM

Are SystemC and TLM-driven design ready to replace RTL? That’s the title of a Design Automation Conference lunch panel moderated by Mark Johnstone, chief technologist for Freescale Semiconductor’ s Flow and Methodology Development Organization...  Read More »
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It's DAC Time Again!

By now, you've probably seen that Cadence is participating quite heavily in DAC this year. Many of my fellow bloggers will be there, as will I. This will make DAC #22 for me, and I'm still looking forward to it... (Parenthetical comment: I know...  Read More »
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