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Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? Well, now there's an easy way to check for that with the checkFiller command: checkFiller -highlight true To get rid...  Read More »
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Friday Fun: Cutting Ties to the Past

In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final...  Read More »
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Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get you all misty eyed? If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have...  Read More »
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Specman 9.2 Preview: Simplifying Generation With ‘Table Constraints’

UPDATE 9/29/2009: Long story short, this feature did not make the 9.2 release . However, if this was of interest to you please contact us so R&D can ask you some questions about what use cases this article made you think about. Apologies for the tease...  Read More »
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ESL And Silicon IP -- Two Sides Of The Same Coin

ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of...  Read More »
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User Interview: What to Expect At 32 nm and Below

Norma Rodriguez, senior member of technical staff at AMD , has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted...  Read More »
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Things You Didn't Know About Virtuoso: RTFM

Wait, don't run away! In this case I really mean " Read The Fantastic Manual ". A recent comment by a reader prompted a spirited internal discussion here at Cadence regarding our Help system. I suddenly realized it had been ages since I...  Read More »
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Functional Verification and EDA "Startups"

A few weeks before DAC, I started working on a blog post about the number of small EDA companies that remain in the functional verification space despite the tough economic times. My interest in completing the entry and publishing on this topic was increased...  Read More »
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Comment Direct From XJTAG, Ltd.

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their trade show strategy -- his message is reproduced in full below. Please post your comments here for the benefit of whole the community, or contact XJTAG apart from this forum...  Read More »
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Verification Panel: Metrics-Driven Approach Requires Mindset Change

Setting up a metrics-driven verification environment isn’t just a matter of tools – it also requires a mindset change along with support from management, according to panelists at the Cadence Ecosystem booth at the Design Automation Conference...  Read More »
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