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Power Issues? Manage Your IR Drop The "Advanced" Way

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions. In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature...  Read More »
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A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four days there when I was back in the office on Friday (July 31). But I returned to a very busy week of actiivties that got bunched up together partly because so many Cadence...  Read More »
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Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’

Nimish Modi is senior vice president for front end research and development at Cadence. In this interview, he discusses Cadence’s front end strategy in such areas as low power, mixed signal, system development, enterprise verification and predictive...  Read More »
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We Interrupt Your Regularly Scheduled Programming...

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso) article this week before I go on vacation, but you know how it is when you're trying to get out of the office for a week. Things just seem to pile up higher...  Read More »
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I Need ASIC IP. Where Can I Find Information?

By Kenneth Chang. The world's best IP ecosystem is ChipEstimate.com . That's what we're hearing every day from our customers. Second to none as a solution, ChipEstimate.com took DAC by storm, with its incredible line up of IP Talks! sessions...  Read More »
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Friday Fun: The Next Generation is Back!

After a bit of a hiatus due to some production issues, we're resuming the series of The Next Generation episodes. This week's episode starts with a review of the previous episode since it was so long ago, and deals with how companies have to make...  Read More »
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Tidbits From TSMC Q209 Earnings Call - 40nm Yield

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...  Read More »
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A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital Systems will be and how this methodology will be the replacement of RTL Synthesis. The term ESL (Electronic System Level) is used as a general term for the new wave of...  Read More »
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Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of systems, prior to RTL coding. These Virtual Prototypes are being used for early software development and architectural analysis. Since there are typically many blocks in...  Read More »
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Advanced Node Panel: Making The Case For Restricted Design Rules

You would think that designers would not welcome restrictions on what they do, but panelists at the recent Design Automation Conference saw restricted design rules (RDRs) as a helpful and necessary step towards 32 nm/28 nm IC design. Panelists from AMD...  Read More »
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