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What's Good About Eye Masks in PCB SI? You'll Need SPB16.2 to See!

Eye masks let you specify the acceptable parameters for what an eye should look like in order to extract clock transmissions and high-speed data to buffer models. The current method of creating and saving eye masks is tedious. SigWave has been enhanced...  Read More »
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Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Since your circuit always runs at low-power, your verification should too. To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively. In some cases that can result in tests...  Read More »
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RTL Power Estimation

RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy...  Read More »
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Requirements for a Student Version of Specman/IES-XL?

Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by the back-to-school season: You may recall a question was posted to Mike Stellfox back in February about the availability of a limited, student version of Specman and IES...  Read More »
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32 nm Test Chips Show Layout 'Context' Matters

Real silicon reveals a lot about how new silicon processes work, and two 32 nm test chips that Cadence recently completed on Common Platform high-k metal gate (HKMG) technology were particularly helpful from a modeling perspective. One conclusion: when...  Read More »
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Friday Fun: A Last-minute ECO

In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on...  Read More »
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What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!

This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. The PSpice engine can identify different sections of a split part and simulate them as a single component by intelligently combining...  Read More »
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User Interview: Challenges Of Analog IP Design And Verification

Kush Gulati is CEO of Cambridge Analog Technologies , a provider of high-performance, low-power analog and mixed-signal IP. In an interview at the recent Design Automation Conference, he talked about the challenges of analog design, modeling, and simulation...  Read More »
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Specman 9.2 Preview: Shortened “When Subtype” Declarations

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes back Yuri Tsoglin from Specman R&D to introduce one of “his” new...  Read More »
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Mixed-Signal Panel: Users Outline Verification Strategies

Mixed-signal verification is a tough challenge, especially when full-chip simulation is needed. But there are solutions, and some of them surfaced at a panel at the Cadence Ecosystem booth at the recent Design Automation Conference. Engineers from SiRF...  Read More »
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