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Tips on Using “vhdlsync” With e+Mixed HDL Simulation

[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch] As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation...  Read More »
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Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

As noted in a prior post , I had the pleasure of attending a DVClub talk given by Brian Bailey entitled "Is it time to declare verification war?". As suggested by the word "war" title, Brian drew many analogies between the legendary...  Read More »
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Intel's Wind River Acquisition - New Help For Multicore SoCs?

Intel’s recent purchase of Wind River Systems is an important move that could have a significant impact on embedded systems design. One possible outcome is better support for multicore system-on-chip (SoC) development. Intel’s $884 million...  Read More »
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Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 1

Yeah, right...in this economy, don't talk to me about real estate. But I'm not talking about home prices, I'm talking about that territory on the screen right in front of you where you spend your day drawing and clicking and arranging and...  Read More »
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Heads-up: Mixed Signal Verification Webinar (June 10)

For those Specmaniacs using the REAL number data type & ports capabilities in Specman, you might be interested in a webinar our analog colleagues are hosting tomorrow (June 10) from 07:00- 8:15 AM (PDT) and a second broadcast at 10:00 -11:15 AM (PDT...  Read More »
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Join us at the Cadence booth at the International Microwave Symposium

If you listened to Tom's advice on this blog two months ago and registered for the International Microwave Symposium or the RFIC symposium, then you should be at the Boston Convention center now enjoying RFIC talks. Please remember that we are waiting...  Read More »
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Q&A Interview: Chris Tice Outlines Cadence System Level Design Strategy

Chris Tice is the senior vice president and general manager for System Design and Verification at Cadence Design Systems. In this interview, he discusses upcoming and ongoing developments with transaction-level IP design, virtual platforms, embedded software...  Read More »
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New IntelliGen Statistics Collection Utilility

As noted in white papers , prior posts , and the Specman documentation, since IntelliGen is a totally new stimulus generator than the original "PGEN", there is usually some amount of effort needed to migrate an existing verification environment...  Read More »
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45 nm Is Turning Point For Model-Based DFM

A recent decision by TSMC to require model-based design for manufacturability (DFM) checks at 45/40 nm may push DFM into more widespread use. It’s coming too late for the several dozen DFM startups that were around a few years ago, but it could...  Read More »
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Porting EDA Applications to Multicore - Part 3

It’s easier to build a multi-threaded application from the ground up than it is to go back and rewrite legacy code – but multi-threading still raises a number of tough challenges. The Cadence Space-Based Router is a case in point. Previous...  Read More »
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