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Building an SOI IP/EDA Infrastructure

My last blog on silicon-on-insulator looked at the low-power benefits of SOI. But performance and power gains are meaningless if you can’t design and manufacture a chip. Fortunately, the needed infrastructure to support SOI design is falling into...  Read More »
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Back to School and Back to the Embedded Software Challenge

The kids have a week of school in the rear view mirror and it's time to get back to the embedded software challenge. Remember when every EDA vendor started saying "Verification is taking 70% of the time on every chip design project"? It...  Read More »
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The Current State of the Art for Physical Synthesis - A Response

I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to...  Read More »
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Green Electronics – Is SOI The Answer?

Silicon-on-insulator (SOI) technology has been used primarily for performance-hungry applications that can justify the additional wafer cost. The SOI Consortium recently launched a “ Simply Greener ” campaign to promote SOI for power savings...  Read More »
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Friday Fun: Tapeout!

Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining...  Read More »
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Let’s Bring Analog Into Low-Power Design Discussion

The discussion about low-power IC design has been focused on digital implementation from RTL on down. We are beginning to move above RTL with tools and methodologies that consider power at a systems level. But what’s not so often discussed is the...  Read More »
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Things You Didn't Know About Virtuoso ADE

After delving into lots of new features in the Virtuoso Schematic Editor, the Library Manager and the Help System , I'd like to turn to our old friend ADE (aka Analog Design Environment , or for those of us who've been around awhile, Analog Artist...  Read More »
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What's Good About Eye Masks in PCB SI? You'll Need SPB16.2 to See!

Eye masks let you specify the acceptable parameters for what an eye should look like in order to extract clock transmissions and high-speed data to buffer models. The current method of creating and saving eye masks is tedious. SigWave has been enhanced...  Read More »
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Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Since your circuit always runs at low-power, your verification should too. To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively. In some cases that can result in tests...  Read More »
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RTL Power Estimation

RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy...  Read More »
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