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Blogs

User Interview: Challenges Of Analog IP Design And Verification

Kush Gulati is CEO of Cambridge Analog Technologies , a provider of high-performance, low-power analog and mixed-signal IP. In an interview at the recent Design Automation Conference, he talked about the challenges of analog design, modeling, and simulation...  Read More »
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What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!

This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. The PSpice engine can identify different sections of a split part and simulate them as a single component by intelligently combining...  Read More »
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Specman 9.2 Preview: Shortened “When Subtype” Declarations

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes back Yuri Tsoglin from Specman R&D to introduce one of “his” new...  Read More »
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Mixed-Signal Panel: Users Outline Verification Strategies

Mixed-signal verification is a tough challenge, especially when full-chip simulation is needed. But there are solutions, and some of them surfaced at a panel at the Cadence Ecosystem booth at the recent Design Automation Conference. Engineers from SiRF...  Read More »
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Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? Well, now there's an easy way to check for that with the checkFiller command: checkFiller -highlight true To get rid...  Read More »
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Friday Fun: Cutting Ties to the Past

In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final...  Read More »
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Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get you all misty eyed? If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have...  Read More »
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Specman 9.2 Preview: Simplifying Generation With ‘Table Constraints’

UPDATE 9/29/2009: Long story short, this feature did not make the 9.2 release . However, if this was of interest to you please contact us so R&D can ask you some questions about what use cases this article made you think about. Apologies for the tease...  Read More »
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ESL And Silicon IP -- Two Sides Of The Same Coin

ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of...  Read More »
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User Interview: What to Expect At 32 nm and Below

Norma Rodriguez, senior member of technical staff at AMD , has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted...  Read More »
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