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Blogs

Must Have Advanced Verification to Achieve Software Signoff

In a recent blog on EDA Graffiti , Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. He identifies...  Read More »
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Specman 9.2 Preview: A Fresh Profile on the Profiler

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes Avi Bloch from Specman R&D to introduce one of “his” new features...  Read More »
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Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

I'm not proud to admit that I reacted with envy to the news that Twitter just received a $1 billion valuation . This story inspired further chatter claiming that if Twitter plays their cards right, they could achieve a $5 billion valuation before...  Read More »
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What's Good About Allegro's Component Placement Changes? - More Features in SPB16.2!

In the SPB16.2 release of Allegro PCB Editor , there are two (2) new very helpful features (among the many others) that assist PCB designers with component placement - Component Alignment and Placement Replication. Component Alignment You can now specify...  Read More »
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CDN Live! Silicon Valley -- A Video Invitation From Cadence CMO John Bruggeman

CDNLive! Silicon Valley , the largest of the CDNLive! Cadence user conferences, will be open for worldwide participation in 2009. This year’s conference is a webinar-based event that allows on-line participation as well as on-site attendance at...  Read More »
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How Do Logic Designers Become Rock Stars?

Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on...  Read More »
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What's the New CMO Mean For Cadence and System Design and Verification?

If you track Cadence stock or other EDA leadership news you undoubtedly know we've hired John Bruggeman as our new Chief Marketing Officer (CMO) and Vice President of Marketing. He's been part of some very dynamic companies, and most recently...  Read More »
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Impressions From A “Virtual” SoC Conference

I attended portions of an EE Times “virtual” system-on-chip (SoC) conference last week, and came away with some observations that I’d like to share. There is some irony here. After years of writing about Cadence and other EDA vendors...  Read More »
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Upcoming ARM Techcon3 or is it Techcon Cubed?

The annual ARM Developers' Conference has been renamed ARM techcon3 , or maybe it is ARM techcon cubed. It will be held October 21-23 at the Santa Clara Convention Center. I'm hoping to get to the keynote by Cypress Semiconductor President and...  Read More »
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User Interview: Running Full Chip Mixed-Signal Simulations

Running full-chip, mixed-signal simulations with sufficient accuracy and speed is a huge challenge for system-on-chip (SoC) designers. But engineers at SiRF , a provider of GPS chipsets and subsystems, have been able to do so, according to Marcelo Silva...  Read More »
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