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Q&A Interview: CMO John Bruggeman Presents Bold Vision For EDA

John Bruggeman , Cadence’s new Chief Marketing Officer (CMO), is bringing a fresh sense of excitement and vision to Cadence and the EDA industry. In this interview he talks about EDA as a “noble cause” that can help save the planet,...  Read More »
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Running Low on Power or Receiving Mixed Signals? Talk to the Expert Users

Everytime my wife and I are looking to buy a big item, we do our research by reading blogs, articles, and customer reviews. I have to tell you, the single best source for information is through customer reviews and testimonials by actual users. Testimonials...  Read More »
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SoC and remodeling cost estimation

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip...  Read More »
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Intrusive Software Debugging: Friend or Foe?

One of the great benefits of working with simulation (RTL, SystemC , or any Virtual Platform) is the ability to provide non-intrusive interactive software debugging. Interactive software debugging provides the control and data access needed to inspect...  Read More »
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Branching Out - My Twitter Experiment

I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue...  Read More »
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Q&A Interview: Kaufman Award Winner Discusses Verification Advances

Dr. Randal Bryant , Dean of Computer Science at Carnegie-Mellon University, will receive the EDA industry’s highest honor – the Phil Kaufman award – in November for his pioneering work in formal verification and simulation. In this interview...  Read More »
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Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back...  Read More »
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User Interview: The Case For High Level Synthesis

One way to gauge the quality of high-level synthesis is to run it on an existing design, and compare the synthesized RTL with the previously hand-generated RTL in power, performance and area. The Industrial Technology Research Institute (ITRI), a Taiwanese...  Read More »
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What's Good About APD's Design Integrity Check? - It's in SPB16.2!

The Cadence IC Packaging tools are complex, flexible tools that allow a designer freedom to create a package substrate layout in a myriad of ways. As a result, it becomes possible to run a particular feature at a time when the database is ill-configured...  Read More »
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Using Vera is like Speaking Sumerian – Who’s Left to Understand?

Just like natural languages, non-standard verification languages can fade away. Sure, ancient Sumerian exists in the Code of Hammurabi , but all modern law is written in living languages. Similarly, verification environments and VIP still exist in Vera...  Read More »
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