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EDA In 1964 – A Look Back At The First DAC

The fact that the 46th annual Design Automation Conference (DAC) is coming up tells us that EDA has been around a lot longer than most people think. What were they talking about back in 1964, the first year for which proceedings are available? (This was...  Read More »
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Tips on Using e Macros to Raise Abstraction and Facilitate Reuse

[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.] As my colleague Hilmar van der Kooij noted in a previous post, e 's "defined as computed" macro capability is a great way to condense repetitive blocks of code...  Read More »
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Embedded Software Plays an Important Role in Low Power Design

At Cadence, there is a big focus on low power design . In the mobile world, power has become the primary design constraint. Everybody knows that dead batteries are no fun. When Cadence IT sent me a new laptop last year, I was very happy to get a machine...  Read More »
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Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator...  Read More »
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Guest Blog: The RF Challenge In Portable Designs

The need for RF integration in consumer electronics presents some tough challenges, says veteran electronics industry editor John Donovan. He notes several emerging approaches that might help ease the challenge. In simpler times most designs were digital...  Read More »
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Low-Power Memory Subsystems Imperative

The figure below was put forth at the recent Denali MemCon, in a speech by Samsung's Dr. Sylvie Kadivar. Memory and Memory Subsystems (MSS), long accused of being the bottleneck to higher system performance, and 'throttling' the MPU with their high latencies...  Read More »
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AOP Discussion on LinkedIn

Hello All, Last week over in the LinkedIn Design Verification Professionals group, a thread came up in the discussion area regarding support for AOP in VERA. The discussion quickly changed to the benefits of AOP for Verification. Unfortunately, for the...  Read More »
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Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in the book – clock gating, multiple threshold optimization, power shutoff, multiple supply voltages etc. What else can you do to reduce power in your design? Or...  Read More »
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Things You Didn't Know About Virtuoso: The View From Above

A few years ago I bought a wonderful book called "Earth From Above". An amazing French photographer has put together a collection of truly unique aerial photographs of all kinds of unusual natural and man-made landscapes. It's fascinating...  Read More »
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Denali MemCon: Huge Hit in a Tough Market

Denali's 2009 Edition of MemCon, its Annual Storage and Memory-Only Conference held 22-24 June in the Hyatt Regency Hotel in Santa Clara, drew approximately 1150 attendees over three days. After Monday's Denali 'Product Tutorial and Training Sessions...  Read More »
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