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Blogs

How To: Purge Interactive Constraints in MMMC Mode

These tips are applicable to the Encounter Digital Implementation System . Back in the good old days, I remember asking designers at the beginning of a silicon virtual prototyping evaluation " Where is your timing constraints file? " Note the...  Read More »
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Specman/IES-XL 9.2 Is Posted - Come And Get It!

We interrupt the Specman 9.2 preview series and ClubT news to announce that 9.2 is now posted on downloads.cadence.com , under the "INCISIV92" umbrella! Hence, for those of you who couldn't get to a recent ClubT, CDNLive, or Incisive Seminar...  Read More »
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Why OVM? John Aynsley of Doulos Has 10 Reasons

Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons...  Read More »
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User Interview: An Under The Hood Look At PDKs

Well-made process design kits (PDKs) are critical for successful IC design, and design teams should keep in touch with PDK technology development, according to Kristin Liu, principal CAD engineer at National Semiconductor . In an interview at the recent...  Read More »
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What's Good About Package Power Integrity? You'll Need SPB16.2 To See!

As clock and data frequencies increase and high-speed systems become ever more densely populated, the distribution of power becomes a major challenge for package power/ground design. To ensure that high-speed systems continue to deliver the required performance...  Read More »
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Cadence’s Andreas Kuehlmann To Head IEEE Council On EDA

With a deep involvement in conferences, publications, educational programs and awards, the IEEE Council on EDA ( CEDA ) is a behind-the-scenes organization that has a large influence on the professional EDA community. Andreas Kuehlmann, Cadence fellow...  Read More »
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Demo: New Signal Tracing Capability in Incisive Enterprise Simulator

One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release. The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal...  Read More »
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Extending Multiple When-Subtypes Simultaneously

[For those of you that didn't / can't make it to a ClubT last week/this week , here is a meaty technical article from guest bloggers Matan Vax (R&D Architect), Yuri Tsoglin (R&D), and Dean D'Mello (CoreComp Architect)] When subtypes...  Read More »
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OpenAccess – So Much To Celebrate, So Much To Do

Two distinct messages emerged from the Silicon Integration Initiative (Si2) OpenAccess Conference last week. One is that the OpenAccess database is a great EDA standards success story, perhaps the biggest such story of all. Another is that there’s...  Read More »
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Physically-Aware Synthesis: This Time it’s Different

RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were...  Read More »
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