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Android System Verification - Part 3

In Part 2 of this series on Android System Verification I provided the basics on how to use the Android emulator console to connect to the built in telnet server and send commands to the emulator. These commands represent hardware events related to power...  Read More »
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New FOSS e Language Project: CFS Vision

There is a new free, open source (FOSS) e language project out there called “CFS Vision” that’s been getting very positive reviews from Specman users as well as our own Application Engineers. For example, their latest release is a really...  Read More »
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Verification Productivity Is Holding Back Electronic System Level Development Advances

There is a controversy brewing in our industry, and I'm about to step into it boldly. I don't expect to end the controversy, since it is about the definition of a three letter acronym. And we all know how much the EDA industry likes to create...  Read More »
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What Is Verification IP Interoperability?

Verification IP (VIP) interoperability is widely discussed these days, but is not often clearly defined. Most people think of VIP interoperability in terms of the work that the Accellera VIP technical subcommittee is doing with respect to the Open Verification...  Read More »
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User Interview: When Formal Is Best For ASIC Verification

Formal verification can serve as the primary verification methodology for an entire ASIC if it meets the right criteria, according to Yogesh Bhagwat, technical lead at Cisco . At the recent CDNLive! Silicon Valley , Bhagwat described the verification...  Read More »
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Tech Tip: Setup Your OVM e Environment So Even Your 16 Year Old Can Use Sequences

A few months ago we introduced the Sequences API in OVM e in the post “ OVM e Sequence API Brings Increased Flexibility ”. As described in that post, the Specman docs, and in code examples, one can use the API to create interesting complex...  Read More »
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User Challenges Drive New Generation of PCB Design Tools

PCB design has been a quiet little corner of the EDA industry that’s typically overshadowed by IC design. But every chip must ultimately go into a package and onto a board, and given the increase in IC complexity and speed, that job can’t...  Read More »
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Highlights From ClubT Hertzelia

Over 125 Verification engineers honored us this past Tuesday by attending the annual "ClubT" in Hertzelia. Here are some of the highlights (and if you were an attendee please post your feedback or follow-up questions in the comments below):...  Read More »
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User Interview: How ECO Handling Works With Equivalence Checking

Vishvabhusan Pati is a senior staff engineer and manager at Qualcomm , where he’s involved in design work and formal and semi-formal design verification. In this Q&A interview, he discusses advantages and limitations of formal equivalence checking...  Read More »
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Guest Blog: Characterizing Process Variability At 32 nm And Below

Process characterization becomes much more complex as feature sizes shrink. In this guest blog Jim Bordelon, president and CTO of Stratosphere Solutions , describes requirements and methodologies for modeling variability at 32 nm and below. Peering under...  Read More »
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