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User Panel: Can Formal Tools Reduce Need For Simulation?

It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort...  Read More »
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Interview With Teradyne on Metric Driven Verification

Welcome to the first TeamMDV blog. We are excited to bring you information, tips, tricks and recommendations all centered around Metric Driven Verification (MDV). To start, here is an interview with Dylan Dobbyn, the verification manager at Teradyne,...  Read More »
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Android System Verification Part 2

In Part 1 of this series on Android System Verification I provided the basics about how to run the Android emulator. When I initially looked at the emulator I was looking for information about available verification techniques, primarily at the system...  Read More »
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User Interview: Formal Analysis Speeds IP Connectivity Verification

The biggest challenge with verification is “always the schedule,” according to Chaitanya Kosaraju, senior design engineer at Xilinx . Thus, anything that can cut verification time without compromising coverage presents a huge advantage. At...  Read More »
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We and Our Competitors Agree (Well, Almost!)

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes Europe this week caught my eye, by Lauro Rizzatti the VP Mktg of EVE. Lauro discussed a survey EVE ran during DAC, where they asked customers how they felt about...  Read More »
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What's Good About Cadence Online Support? – Here’s My List!

My good friend and fellow blogger - Bob Dwyer - recently posted on the new Cadence Online Support . Bob did a terrific job and I encourage you to read his post - Find, Fix And Learn With Cadence Online Support Bob's provided screenshots, highlights...  Read More »
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Panel Question: Should Designers Do Their Own Verification?

One question that prompted a lively discussion at the recent Cadence Mixed-Signal Design Summit was whether design engineers should do their own verification. This is a particularly good question for analog and mixed-signal design, where the tradition...  Read More »
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IntelliGen Lab Now Live on Xuropa - See What You Are Missing!

Team Specman guesstimates that a majority of users have migrated to "IntelliGen" -- the all new, Aspect-Oriented generation engine inside of Specman and IES-XL, and/or they are in the process of adopting IntelliGen now. However, in case your...  Read More »
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“Software Signoff” Raises Many Questions

At a discussion at the ICCAD conference last week, EDA notables Jim Hogan and Paul McLellan talked about “ what EDA needs to change for 2020 success. ” One topic they emphasized is “software signoff,” and they encouraged those...  Read More »
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Android System Verification Part 1

From time to time I hear or read stories about how engineers find ways to apply Specman to verification problems that are outside of normal RTL verification. Often times they are about connecting Specman to a post-silicon environment such as a physical...  Read More »
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