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CES Provides Wake-Up Call for EDA

Since consumer electronics is the primary driver for IC and systems design, what happens at the Consumer Electronics Show (CES) should interest the EDA community. Any trends in new consumer devices will point the way to design challenges EDA tools will...  Read More »
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AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders...  Read More »
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Behind Accellera’s Vote For OVM-Based Standardization

As noted in a recent Cadence blog by Tom Anderson, the Accellera Verification IP (VIP) Technical Subcomittee has voted to make the Open Verification Methodology ( OVM ) the basis of its upcoming “Universal Verification Methodology” (UVM) standard...  Read More »
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What's Good About Allegro Placement Replication / Fine Tuning? - Look to SPB16.3 And See!

Placement replication was introduced in Allegro PCB Editor SPB16.2. At that time, the application was limited to replication of component placement. The SPB16.3 release introduces the support of etch circuits (shapes, clines, vias) as well as ease of...  Read More »
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Low Power DDR Options -- From the Trenches

by Marc Greenberg, Director of Technical Marketing, Denali Software Momentum for LPDDR2 is building. It's mostly in the mobile space, and it's been in the general area of Handsets, MIDs, and other mobile devices. Both high-end and low-end handset customers...  Read More »
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Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and...  Read More »
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Back to Work in 2010

It's back to work in 2010. Thanks for all the great feedback in 2009. I plan to continue to bring readers interesting material about System Design and Verification in 2010. When I got back to work this week I fired up an openSUSE 10.2 VMWare image...  Read More »
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Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the...  Read More »
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Trying to Figure Out Social Media? Ron Ploof Says "Read This First"

Left to Right: Ron Ploof, Bob Dwyer Photo Credit: brillianthue "As a New Media evangelist...I've been able to categorize those reactions into three different personality types: The 'Get-Its,' the 'Traditionals,' and my favorite...  Read More »
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Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

I was recently part of an industry wide interview conducted by Clive "Max" Maxfield of TechBites . Max is trying to uncover the reality behind the apparent trend to move to the high level abstraction of transactions for design and verification...  Read More »
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