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Industry Insights Blog Aims for Broad Perspectives
By Richard Goering
on March 31, 2009
Welcome to the new Industry Insights site of the Cadence Community ! In this site, we’ll explore issues and technologies of interest to IC and systems designers and design managers from an industry-wide perspective. This blog will offer timely commentary...
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Filed under: EDA, SCDesign, EETimes, blogs, forums, Industry Insights
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Software Verification or Validation With ISX?
By Team ESL
on March 30, 2009
[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.] At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title "...
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Filed under: System Design and Verification, ISX, verification, ARM, validation, embedded world conference
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Virtuoso, the SATs, and The Dark Knight - Part I
By Michael Kelly
on March 30, 2009
You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight. Well, first of all, it has only been in the past few years (so this, obviously isn’t something I’ve had to do!), but today's high school students now...
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Filed under: Custom IC Design, Virtuoso, Virtuoso IC 6.1.3
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DVCon '09 SaaS Panel Thoughts, Part 3
By Joseph Hupcey III
on March 30, 2009
In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were: Security ( the focus of Part 2 of this series ) EDA applications that can clearly benefit from...
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Comments (2)
Filed under: Functional Verification, DVcon, SaaS, Xuropa, Harry The ASIC Guy
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Automated Digital Block Implementation Using Virtuoso
By John Wilkosz
on March 27, 2009
Have you ever found yourself laying out a digital block in Virtuoso where you have so many standard cells to place and route that you wish you could use an automated tool to place and route those cells? Maybe you even at one point considered using a Big...
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Comments (5)
Filed under: Custom IC Design, Virtuoso, VSR, Virtuoso Custom Placer, VCP
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Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"
By Michael Jacobs
on March 27, 2009
Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm...
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Filed under: Digital Implementation, Encounter Timing System, encounter, EDN
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IEEE 1801 - They Were That Close
By Steven Carlson
on March 27, 2009
I always get this wry smile on my face when I see it happen. An effort that is launched with lofty ideals and worthy goals, but with those predictable pitfalls that will, in the end, park the car on the train tracks, just waiting for the next locomotive...
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Filed under: Logic Design, Common Power Format, IEEE 1801
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Is Software Engineering Engineering? You Decide!
By Jason Andrews
on March 27, 2009
Last night when I was waiting for my daughter to finish orchestra rehearsal (she is a violin player in the Greater Twin Cities Youth Symphony ) I was reading an article in the latest issue of Communications of the ACM with the title "Is Software...
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Filed under: System Design and Verification, design metrics, software engineering, failure tolerance
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Friday Fun: TNG Team Facing Real Logic Design Issues
By Jack Erickson
on March 27, 2009
If you've been following this series, first thank you! But where the early episodes may have seemed to be about the fun and glamor of chip design, we start to show some real issues facing chip design projects. In episode 5, we have the verification...
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Filed under: Logic Design, chip design, The Next Generation, project management
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Calculating Large Signal Phase Noise Using Transient Noise Analysis
By Alan Whittaker
on March 26, 2009
My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group. We support Cadence's Technical Field Organization (the AEs) and Cadence customers during the introduction and adoption of new and advanced EDA technologies. I'll...
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Comments (1)
Filed under: Circuit Design, Custom IC Design, RF Design, MMSIM, Simulators, PLL
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