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Blogs

Analyzing Distortion With Spectre RF

Greetings, In the previous appends, we looked at using Shooting Newton Periodic Steady-State analysis to analyze analog circuits. In this append, we will look at using Harmonic Balance Periodic Steady-State, HBPSS, to analyze analog circuits. HBPSS is...  Read More »
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Debug Emerges As Biggest Verification Bottleneck

We’ve all heard that functional verification takes 60 to 70 percent of the design cycle, but what’s not often discussed is what, exactly, takes up all that verification time. For a growing number of design and verification teams, the biggest...  Read More »
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Encounter How-To: Selecting Objects By Pointer With dbGet And dbSelectObj

I just got back from a trip to California where I met with a couple of customers and presented database access with dbGet in the Encounter Digital Implementation System (EDI for short). I took notes on the questions that came up- in particular those common...  Read More »
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A Holiday Gift For Verification Projects Adopting MDV

Submitted By MDV Team Member – John Nehls Architect and Team Lead for MDV Solutions Deployment Would you like to be doing more with your Enterprise Manager environment but just don’t have the time to figure out how to do it? Maybe things like...  Read More »
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Intel TV Interview: Parallelizing Legacy EDA Applications

Can EDA vendors parallelize millions of lines of legacy code, or do they need to rewrite everything in order to run on multicore and many-core platforms? In a Dec. 8 interview for Intel Software Network TV , Tom Spyrou, distinguished engineer at Cadence...  Read More »
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What's Good About The SPB16.3 Release? It's Here - Download It now!

The SPB16.3 release is now available (actually, it was available last week from the Cadence software downloads site at - http://downloads.cadence.com/ ). Where has the year gone! It seems like only yesterday I was blogging about all the cool new SPB16...  Read More »
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Attention RTL Compiler Customers! RC 9.1.200 Is Here

Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly...  Read More »
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Are You Playing with a Full Deck?

A professional gambler confidently place bets because she know the odds, but she would be crazy to play at a table that didn’t use a full deck because the odds change in an unknown way. If you use a simulator that doesn’t enable low-power...  Read More »
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Things You Didn't Know About Virtuoso: IC 6.1.4 (VSE L)

By now, you've surely heard the news. And if you haven't yet, you have now. Virtuoso IC 6.1.4 is now available! Huzzah, huzzah! I was (and still am) planning to do my next series of "Things You Didn't Know" about ADE XL, but for...  Read More »
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Q&A Interview: New IEEE DASC Chair Discusses EDA Standards

Stan Krolikoski, group director for standards and ecosystems at Cadence, has been elected chair of the IEEE Design Automation Standards Committee ( DASC ), which oversees all EDA-related IEEE standards activities. In this interview he discusses the role...  Read More »
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