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Blogs

EDA Outlook 2010: A Cost-Driven Market

The worst recession of modern times may be over, but the changes it is leaving in its wake will persist. For surviving semiconductor and systems companies, a new top priority has emerged – controlling and reducing both design costs (implementation...  Read More »
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NPORT S-Parameter Model Enhancements

In MMSIM 7.2, two new parameters have been added to the Spectre nport primitive: datatrunc and causality . In MMSIM 7.1, passivity checking was added. The nport now has causality correction, passivity checking and enforcement, and the ability to remove...  Read More »
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Adam’s Verification Top 10 In '10

I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here...  Read More »
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Android System Verification Part 5

In the previous article I introduced the use of Specman for generating sequences of commands to send to the Android emulator. I demonstrated a better way to generate hardware stimulus compared to using the original telnet connection to the Android console...  Read More »
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My Wish List For The New Decade

Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is...  Read More »
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What's Good About Reflection?

What's good about it is that we don't need to reflect occasionally. We can reflect on our lives often. During this Christmas and Hanukkah time, many Judeo–Christian people celebrate the spirituality of the season by reflecting on family...  Read More »
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Notable EDA Blog Postings For 2009

This is the time of year when everybody has lists – and here’s one that may be a little different. Below are some notable blog postings from various external (non-Cadence) blogs in 2009. They’re listed in chronological order with no...  Read More »
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Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non...  Read More »
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Happy Holidays - OVM on The Path to Standardization

I've just heard that the Accellera VIP Technical Subcommittee (TSC) has voted to make the OVM the base for their Universal Verification Methodology (UVM) standard and, in spite of the holidays, I’m so happy that I have to blog about it. When...  Read More »
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Wrapping Up 2009 With Some Reflections

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of...  Read More »
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