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Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and e put me in a reflective mood about my own evolving opinions. My hands-on experience with Specman is minimal; back in my 0-In applications days I co-developed a joint...  Read More »
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Running Incisive on Ubuntu Linux

Ubuntu is by many accounts the most popular and the easiest to use Linux distribution for the desktop. Unfortunately for Linux enthusiasts, Cadence tends to follow the EDA Industry OS Roadmap when selecting operating systems to support. I would guess...  Read More »
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DVCon OVM Panelists: Easing The Debug Challenge

The good news about the Open Verification Methodology ( OVM ) and the advanced verification techniques it supports is that verification engineers are now finding more bugs than ever. The bad news is that the bottleneck is shifting to debugging. What are...  Read More »
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What's Good About Capture’s Auto-Wiring? You’ll Need The SPB16.3 Release to See!

Just a brief post this week to highlight one of the new SPB16.3 features in Allegro Design Entry CIS . In complex designs containing a large number of parts, the task of wiring the parts together is often a time consuming and tedious task. Wiring multiple...  Read More »
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Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs". In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like...  Read More »
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Things You Didn't Know About Virtuoso: Thumbnails

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence. A couple of months ago we came out with this great new Virtuoso software release (IC 6.1.4) . So, despite my best efforts to get you to use the recently-opened files...  Read More »
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Analog Behavioral Modeling - What Language Do You Speak?

An increasing number of mixed-signal design teams are contemplating adding analog behavioral modeling to their repertoire in order to achieve reasonable simulation speeds. Utilizing analog behavioral models can yield simulation performance improvements...  Read More »
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DVCon Panel: Three Ways To Minimize Verification Effort

With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three...  Read More »
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DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating...  Read More »
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DVCon Panel: Why Verification Engineers Are “Sleepless”

I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives...  Read More »
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