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Momentum Grows for IP Power Modeling Standard
By Richard Goering
on April 15, 2009
With no standard way to represent power consumption for silicon IP, early IC power estimation can be difficult. But help may be on the way, as the SPIRIT Consortium and its members, including Cadence, discuss possible approaches to IP power modeling....
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Filed under: encounter digital implementation system, Industry Insights, IP-XACT, SPIRIT consortium
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Part 1 - Constraint-driven Physical Design Speeds Custom IC Design Convergence
By Craig Thompson
on April 15, 2009
In this introductory Part I of V of this blog I will discuss the advanced node design challenges impacting CIC design convergence and the solutions to achieve expedited physical implementation convergence. As designers move to 65nm technologies and below...
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Filed under: CAA, chip optimizer, CMP, Connectivity-driven, Constraint-driven, Custom IC Design, DFM, DFY, IC 6.1, IC 6.1.4, Litho, space based router, Virtuoso IC 6.1.3, Virtuoso Space-based Router, VSR
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Industry Discussion about High Level Synthesis
By Steven Brown
on April 14, 2009
Many of you know that Richard Goering has joined Cadence and now writes a blog called Industry Insights . Just last week Richard posted a blog about High Level Synthesis that generated some debate about what's new. Check it out for yourself, and add...
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Filed under: CTOS, High-Level Synthesis, incisive c-to-silicon, Richard Goering, System Design and Verification, TLM
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Survey Results For "Booth-Centric" vs. "Paper Centric" Shows
By Joseph Hupcey III
on April 14, 2009
In my last post I shared how my annual tour of the tour of the ESC show floor inspired me to ask the community their preferences on trade show formats. Since I'm not certain how persistent these free survey sites are, allow me to replicate a snapshot...
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Filed under: CDNLive, CDNLive San Jose 2008, DAC, DVcon, ESC, events, Functional Verification, Specman, Xuropa
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Noise Induced Double Clocking Explained
By Michael Jacobs
on April 14, 2009
In my previous blog on noise analysis accuracy , I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise...
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Filed under: CadMOS, CeltIC, Digital Implementation, double clocking, encounter, Enouter Timing System
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Making Sense of Version Numbers
By Team FED
on April 14, 2009
By Matt Rardon Synthesis Solutions Your Cadence contact tells you that the fix you need is in RC 8.1.201. You ask your internal contact what version of RTL Compiler is installed and you are told that it is 08.10-s203_1. Why the discrepancy? Is this the...
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Filed under: conformal, Logic Design, Matt Rardon, RTL compiler, versions
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IC Design vs. Manufacturing Objectives - Can Both Be Achieved Concurrently?
By Craig Thompson
on April 13, 2009
IC designers and foundries typically have different objectives. IC designers want to achieve the greatest performance while performing the least amount of guard-banding. Schedules and predictability are also paramount concerns for designers. IC Foundries...
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Filed under: Chip finishing, custom design technology, Custom IC Design, IC 6.1.4, Physical placement and layout, Virtuoso IC 6.1.3, Virtuoso Space-based Router
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What Cadence Has Learned About SaaS
By Richard Goering
on April 13, 2009
Software as a Service (SaaS) for EDA applications has been a hot topic lately, but most of the discussion has been theoretical. Cadence Design Systems’ implementation of SaaS brings some practical experience to the discussion. Software as a Service...
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Filed under: CAD, EDA, HDS, Hosted Design Solutions, Industry Insights, SaaS
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Performance-Aware e Coding Guidelines – Part 3
By Team Specman
on April 13, 2009
The constraint solver is a powerful and fun to use tool. Actually, it is so much fun that sometimes people tend to use it in cases where generation is not required. Of course, like any other algorithmic engine, the “price” of using the constraint...
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Filed under: e, Functional Verification, IES, IES-XL, Incisive Enterprise Simulator (IES), performance, Specman, specman elite, tech tips
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Friday Fun: Caveman Finds Cadence
By Jack Erickson
on April 10, 2009
For those of you new to this series that want to come up to speed quickly, the best bet is to check out the "Notes" for each episode over on the "The Next Generation" Facebook page . Become a fan! After last week's desparation...
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Filed under: AE, caveman, chip planning, incyte, Logic Design, The Next Generation
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