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Blogs

OVM Community Contributions: Wildly Popular And Clearly Essential

A couple of weeks ago, before going to bed one night I checked the statistics for the OVM World site. What I saw was really cool - exactly 10,000 registered users at the moment I looked! Being a social media guy these days, the first things I did was...  Read More »
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DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many...  Read More »
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Toyota Prius 2005: An Early Warning About Verification

The news headlines have been full of reports about the 2010 Toyota Prius, which apparently has a software bug that causes braking problems on bumpy roads. What most reports don’t say is that some 2004 and 2005 Toyota Prius cars also had a software...  Read More »
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Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling...  Read More »
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What's Good About ASA Schematics? Numerous Improvements in The SPB16.3 Release!

Allegro System Architect (ASA) also known as System Connectivity Manager (SCM) allows you to generate a schematic for your logical design. You can use the generated schematic for documentation purposes, or for communicating various aspects of the design...  Read More »
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DesignCon Panel Offers New Insights On Social Media

I thought I was fairly knowledgeable about blogging, Twitter, and other aspects of “social media,” but I learned a lot from a panel at the recent DesignCon 2010 . Entitled “Social media – do we really have to do it?” the...  Read More »
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Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

The most common metrics used in current metric driven verification (MDV) flows are various forms of code coverage (block, FSM, toggle etc.), assertion coverage, and functional coverage. As many of you know, all of these can be collected into Enterprise...  Read More »
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Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis,...  Read More »
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IBM/Cadence Collaboration Points To “Next Generation” EDA

Embedded software development and hardware/software integration have become primary bottlenecks for system-on-chip (SoC) projects. Still, most EDA tools remain exclusively focused on hardware design, while software development tools have no understanding...  Read More »
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An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. Then they can add new functionality on...  Read More »
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