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ARM AMBA 4 Protocol And VIP – A Closer Look

ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's...  Read More »
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UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face-to-face meeting held last week in Massachusetts. But with the steady stream of tweets coming from several of those who did attend, I almost felt as if I were there...  Read More »
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Bringing MEMS Design To The Mainstream

Micro-electrical mechanical systems ( MEMS ) have been around for years, and have found their way into high-volume applications such as automobile air bag controllers, GPS systems, and inkjet print heads. But MEMS devices such as accelerometers, gyroscopes...  Read More »
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Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK] Messaging is important for two main reasons: It is essential for debugging It can greatly impact simulation performance This is why Specman has a messaging infrastructure...  Read More »
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What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release These enhancements will improve your experience with analyzing simulation results especially for dense designs. These features include: Easy to...  Read More »
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Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient

Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to...  Read More »
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Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements

I'm not going to beat around the bush here. I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4. I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that...  Read More »
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Challenging Misconceptions About Verification Languages

One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way...  Read More »
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VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol. Here is the official announcement, which...  Read More »
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When Will We Move From RTL to TLM? I Need to Know!

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point...  Read More »
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