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Flash Memory Summit: 3D NAND Flash Faces Cost, Reliability Challenges

3D NAND Flash architectures will provide the best option for increasing storage densities in future years, according to panelists at a plenary session at the Flash Memory Summit Aug. 5, 2014. But given the large manufacturing investment required, and...  Read More »
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Disk Drive’s Days Might be Numbered: Woz

Apple cofounder Steve Wozniak sees solid state memories replacing the hard disk drive almost completely. ...  Read More »
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Whiteboard Wednesdays - The Evolution of NAND Flash

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need for advanced error correction. Lou also details the Berlekamp Chaudhuri Hocquenghem (BCH) algorithm. Learn how this algorithm is implemented and how engineers are...  Read More »
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New OrCAD Offerings Zero in on Engineering Productivity Challenges

OrCAD just announced three new PCB design software products that attack less-glamorous but still crucial areas of PCB engineering productivity. ...  Read More »
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Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Power signoff isn't just about digital logic—analog and custom digital blocks in SoCs need power integrity analysis as well. That's why Cadence today (Aug. 4, 2014) is introducing the Voltus-Fi Custom Power Integrity Solution, which provides...  Read More »
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Verification IP: 7 Things I Learned By Browsing Cadence Online Support Last Month

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more thoroughly, and with less effort. While innovating and providing great products and technologies, the VIP team at Cadence also believes that it is important to keep creating...  Read More »
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Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting Via Arrays

Manufacturability and quality of the power and ground feeds for your package are always a big concern for all of us. When you have multiple plane layers, connecting them together with reinforcing vias is a great idea, with just one problem: how do you...  Read More »
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FinFETs, Advanced Process Nodes, and Parasitic Extraction

Cadence's Hitendra Divecha talks about advanced-node and FinFET design challenges and how to manage parasitic extraction....  Read More »
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Designer View – How Emulation/Virtual Prototyping “Hybrid” Speeds Software Development

200X. That's the number with which Moshe Berkovich, senior engineer at fabless semiconductor provider CSR , started a 15-minute talk that is now a recorded presentation on Cadence.com. And 200X is the performance improvement that his team was able...  Read More »
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New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog and UVM Environments

There is always a demand for learning something simply and quickly on your own in some corner of the world. The big challenge that I have faced with learning is how to find the right learning vehicle that helps me discover what I didn't already know...  Read More »
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