|
Friday Fun: Even a Marketing Guy Can Use InCyte!
By Jack Erickson
on April 24, 2009
In this week's episode, Gronk, the unfrozen caveman marketing guy, discovers how easy it is to explore a new power architecture and get both technical and economic estimates using the InCyte software. Meanwhile, the design team realizes that what...
Read More »
Comments (0)
Filed under: caveman, chip planning, incyte, Logic Design, marketing, Power Shut-Off, The Next Generation
|
 |
|
A Glimpse Into The Future Of High-Level Synthesis
By Richard Goering
on April 23, 2009
High-level synthesis (HLS) is already in production use today, but other exciting and complementary new technologies and capabilities are coming in the future. Recently I talked with Michael “Mac” McNamara and Luciano Lavagno – both...
Read More »
Comments (0)
Filed under: BONES, C-toSilicon, DATE, ESL, High-level Synthesis, HLS, Industry Insights, RTL, TLM
|
|
|
|
What's Good About Social Networking? Boomer Adoption up, Gen Y Flat
By Gerald "Jerry" Grzenia
on April 22, 2009
I decided to switch gears a bit and write about an interesting article I read in Electronic Engineering Times (April 6, 2009) - " Social networking: Boomer adoption Up, Gen Y Flat " by Junko Yoshida. What I found fascinating is that us "old...
Read More »
Comments (0)
Filed under: Baby Boomers, EE Times, Generation Y, PCB design, Social Networking
|
|
|
|
|
TSMC Views R&D As Ticket Out Of Recession
By Richard Goering
on April 22, 2009
What do you do if your revenues decline nearly 60 percent in the space of two quarters? If you’re TSMC, you hire more R&D people, expand your focus beyond conventional SoCs, and work to innovate your way out of the recession. TSMC’s “can...
Read More »
Comments (0)
Filed under: EDA, Industry Insights, R&D, Recession, TMSC
|
|
|
|
Spectre RF By Any Other Name ...
By Arthur Schaldenbrand
on April 22, 2009
It has been a while since I last appende d , hope you are well! It was a little bit difficult to come up with a subject to write about and then recently I was in a meeting where we were talking about transient noise analysis. A designer was discussing...
Read More »
Comments (5)
Filed under: ADC, DAC, RF design, Spectre RF
|
|
|
|
Setting VIVA Waveform Color Defaults When Using ADE
By David Neilson
on April 21, 2009
I found myself getting a little bit frustrated with some of the default colors that would come up in the VIVA waveform tool while I was plotting from the Analog Design Environment (ADE). After working with Kabir, the Product Engineer for VIVA, I discovered...
Read More »
Comments (5)
Filed under: MMSIM71, RF design, Spectre, spectreRF, Virtuoso Spectre
|
|
|
|
|
A Qualcomm Perspective on 3D ICs
By Richard Goering
on April 20, 2009
3D integration is a promising new technology that can potentially save space and power by stacking die in 3 dimensions. I recently spoke with Riko Radojcic, Qualcomm design lead for TSS (Through Silicon Stacking – Qualcomm’s term for 3D ICs...
Read More »
Comments (1)
Filed under: 3D ICs, DATE, Industry Insights, Qualcomm, TSS, TSVs
|
|
|
|
OpenAccess, Its Just a Database…
By Thomas Costas
on April 20, 2009
I suspect that in another year we’ll all stop talking about OpenAccess (OA) like it is something special and treat it the way it should be, that it is just another database. Having said that, I know I’m going to get plenty of email about my...
Read More »
Comments (0)
Filed under: custom design technology, Custom IC Design, ecosystem, PDK, Process Design Kit, Virtuoso, Virtuoso Analog Design Environment
|
|
|
|
CtoS support of Multiple Clocks
By Team ESL
on April 20, 2009
In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support multiple threads in a similar way that traditional Hardware Description Languages (HDLs) support multiple processes. There are many applications, such as multi...
Read More »
Comments (0)
Filed under: clock, clocking, CTOS, C-to-Silicon Compiler, High-Level Synthesis, System Design & Verification, SystemC
|
|
|
|
System-level Low Power Techtorials/Workshops Off To A Great Start!
By Steve Svoboda
on April 20, 2009
Back in my 24 March blog I mentioned how Cadence was kicking off a major techtorial/workshop series across North America on low power chip design, using the newest Cadence tools at the ESL/System/Chip Architecture level. Last week we concluded the first...
Read More »
Comments (0)
Filed under: C-to-Silicon, ESL, incyte, System Design and Verification, techtorial, workshop
|
Community GuidelinesThe Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines. |