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CDNLive Munich Guide for Specmaniacs
By Team Specman
on May 11, 2009
Good news for Specmaniacs based in the EU: next week from May 18-20 is the annual CDNLive! event in Munich. An overview of the conference with info on how to register is here: http://www.cadence.com/cdnlive/eu/2009/pages/default.aspx Naturally CDNLive...
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Filed under: Functional Verification, OVM, CDNLive, techtorial, Cadence VIP portfolio, e, Specman, OVM e, Mike Stellfox
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Guest Blog: New IEEE P1647 Chair On What’s Next For e Language
By Richard Goering
on May 11, 2009
Darren Galpin, senior staff engineer at Infineon , recently became chair of the IEEE P1647 working group for e language standardization. In this guest blog, he describes what’s coming up for the 2010 revision of the verification language, and calls...
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Filed under: Industry Insights, SystemC, TLM, ieee1647, infineon, globetech solutions, specman
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Friday Fun: The Secrets of EDA Marketing
By Jack Erickson
on May 8, 2009
A little context for this episode - the old EDA company sent in their execs in the previous episode - so here we have Charlene bringing her marketing guy along to try to salvage things with Chip. Chip is annoyed, but decides to have them be useful. Big...
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Filed under: Logic Design, marketing, The Next Generation
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Cross Currents in Memory Market Signal Changes Ahead
By Denali Blog
on May 7, 2009
No one can say with any certainty, but... Recent improvements in DRAM and NAND pricing, a firming of demand, and a 'the bloom is off the rose' attitude toward the 'TMC DRAM Salvation Initiative', have all pointed to perhaps a better memory future, after...
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Modeling Interfaces with C-to-Silicon Compiler
By Team ESL
on May 7, 2009
Users of ESL tools are curious about the procedure for handling the interface to a bus or other communicaton protocol in a High Level Synthesis environment. This is usually formulated in the following question: “How do we take into account the interface...
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Filed under: System Design and Verification, C-to-Silicon, SystemC analysis, CTOS, TLM 2.0, modeling, high level synthesis, transaction level modeling, dma, hls
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Tracing TLM 2.0 Activity in an ESL Design – Part 3
By George Frazier
on May 7, 2009
Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM 2.0 transaction data ( http://www.systemc.org ). In this post, we’ll explore the data in the Simvision Waveform Viewer, the Transaction Explorer, and with TxE...
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Filed under: ESL, TLM, System Design & Verification, Simvision
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CDNLive! Silicon Valley Call for Papers Abstract Submission Deadline is Looming!
By Jack Erickson
on May 7, 2009
Just a quick head's up - the deadline for abstract submission for the Silicon Valley CDNLive! is May 15 . The conference will take place October 1-2 at the Santa Clara Marriott. You can go here to submit an abstract . Check out some of the past Logic...
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Filed under: Logic Design, CDNLive!, papers
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e Coding Made Easy with the “DVT” Integrated Development Environment
By Team Specman
on May 6, 2009
Specmaniacs everywhere should be aware of a great, full-featured integrated development environment (IDE) available for e language coding from long time Verification Alliance partner AMIQ . In today's post, Team Specman invites the founder of AMIQ...
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Filed under: Functional Verification, OVM, eRM, SystemVerilog, CDNLive, eclipse, e, Specman, IEEE 1647, OVM e, OVM SV, specman elite, AMIQ
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It's Not Too Early to Think About DAC 2009
By Jason Andrews
on May 6, 2009
Even though it's still a couple of months off, it's not too early to think about DAC 2009 . This year's conference will be held July 26-31 at the Moscone Center in San Francisco. The technical program was announced this week, and after a couple...
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Filed under: System Design and Verification, DAC 2009, hardware-dependent software
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Q&A Interview: Charlie Huang, Cadence Chief Strategy Officer
By Richard Goering
on May 6, 2009
Charlie Huang is chief strategy officer and acting CTO at Cadence Design Systems. In this Q&A interview, he talks about his background and his role at Cadence, discusses technology development in such areas as verification, low power, ESL, and mixed...
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Filed under: EDA, Industry Insights, ESL, FinFets, Digital Design, SoC
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