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When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s...  Read More »
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My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12 th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly...  Read More »
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Video Demo: Your Maiden Voyage Across OCEAN

I still remember my first encounter with OCEAN. It was 2002 and my co-worker had asked me to run a simple test for him. I sat in my cube, ruffling through our user guides, trying to quickly learn just enough to do the task at hand. The story ended happily...  Read More »
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ISQED Keynote: Putting Some Numbers To Cost-Aware Design

We've all heard about the escalating costs of system-on-chip (SoC) development. But what are the costs, and what are the potential savings? Steve Glaser, corporate vice president of strategic development at Cadence, filled in some of those numbers...  Read More »
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Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes useful to be able to access a memory or peripheral from a normal user space program. This can help determine if the hardware is connected properly and it can help...  Read More »
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What Madonna Can Teach You About Chip Design

Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other...  Read More »
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What's Good About Taray? Quite a Bit Actually!

You've probably read about all the buzz in the EDA news this week - " Cadence acquires FPGA-focused EDA startup " and here . " Cadence buys Taray in time for 28nm FPGAs " " Cadence Acquires FPGA Tool Firm Taray " "...  Read More »
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Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the discussion going on at a recent Accellera TSC meeting just by reading the tweets from the participants. That experience got me thinking about how much social media has changed...  Read More »
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Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source software (FOSS) "CFS Vision" project. The CFS Vision team has now posted this brief introductory video on the Java-based e VC Generator utility described in...  Read More »
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TeamAllegro Spices Up SNUG With Allegro PCB SI

Allegro PCB SI has supported multiple simulation engines for well over seven years. Other than the native TLsim engine, HSpice has been one of the more popular simulation engine choices. This year at SNUG, we have been invited to meet with HSpice users...  Read More »
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