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Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source software (FOSS) "CFS Vision" project. The CFS Vision team has now posted this brief introductory video on the Java-based e VC Generator utility described in...  Read More »
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TeamAllegro Spices Up SNUG With Allegro PCB SI

Allegro PCB SI has supported multiple simulation engines for well over seven years. Other than the native TLsim engine, HSpice has been one of the more popular simulation engine choices. This year at SNUG, we have been invited to meet with HSpice users...  Read More »
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Q&A: What Cadence Has Learned About High Level Synthesis

With the recent release of Cadence C-to-Silicon Compiler, Cadence has joined the rapidly growing high-level synthesis (HLS) marketplace. In this interview Mike "Mac" McNamara, vice president and general manager of the Cadence Systems Software...  Read More »
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Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in my opinion a "must have" for any marketer and executive in the EDA and the semiconductor industries. The book is called " Chips and Change - How Crisis Reshapes...  Read More »
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Exceed On Demand And Virtuoso IC6.1

Many of our customers use our Virtuoso software in combination with the windows emulation product from OpenText named "Exceed on Demand". To maximize performance between the two tools, we have some recommendations: For IC6.1.4 and Exceed on...  Read More »
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An Inside Look At The Unified Coverage Interoperability Standard

A standard is quietly emerging to help verification engineers deal with coverage information from different sources - and if that's a concern for you, there's still time to get involved. The Accellera Unified Coverage Interoperability Standard...  Read More »
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What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen!

This week, I'm taking a brief break from the usual PCB solution/product technical discussions and focusing on a very interesting capability used with the Cadence Allegro PCB Editor product. You can read all the details from this article - Integrated...  Read More »
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SystemC AMS – A New Proposal For Mixed-Signal Verification

In an effort driven by European semiconductor companies and universities, the Open SystemC Initiative ( OSCI ) last week announced the first version of the SystemC analog/mixed-signal language standard, AMS 1.0. Since Cadence is the industry leader in...  Read More »
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Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group in the UK] Building on the Part 1 introduction to Specman’s messaging built-in infrastructure , allow me to share some tips on how to programmatically control and scale...  Read More »
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ARM AMBA 4 Protocol And VIP – A Closer Look

ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's...  Read More »
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