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Friday Fun: Cutting Ties to the Past
By Jack Erickson
on August 28, 2009
In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final...
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Filed under: friday fun, Logic Design, Static timing analysis, The Next Generation
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Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution
By Joseph Hupcey III
on August 27, 2009
Does the union of verification automation and IT+source code management tools get you all misty eyed? If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have...
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Filed under: DAC, Enterprise Manager, Enterprise Planner, Functional Verification, IBM, IES-XL, Incisive Enterprise Simulator (IES), MDV, metric driven verification (MDV), Rational, Tivoli
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Specman 9.2 Preview: Simplifying Generation With ‘Table Constraints’
By Team Specman
on August 27, 2009
UPDATE 9/29/2009: Long story short, this feature did not make the 9.2 release . However, if this was of interest to you please contact us so R&D can ask you some questions about what use cases this article made you think about. Apologies for the tease...
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Filed under: AOP, Aspect Oriented Programming, e, Functional Verification, IES-XL, Incisive Enterprise Simulator (IES), IntelliGen, Specman
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ESL And Silicon IP -- Two Sides Of The Same Coin
By Richard Goering
on August 27, 2009
ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of...
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Filed under: chip estimate, ESL, Industry Insights, System C, TLM
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User Interview: What to Expect At 32 nm and Below
By Richard Goering
on August 26, 2009
Norma Rodriguez, senior member of technical staff at AMD , has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted...
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Filed under: advanced node, AMD, DAC DFM, Global Foundries, Industry Insights
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Things You Didn't Know About Virtuoso: RTFM
By Stacy Whiteman
on August 25, 2009
Wait, don't run away! In this case I really mean " Read The Fantastic Manual ". A recent comment by a reader prompted a spirited internal discussion here at Cadence regarding our Help system. I suddenly realized it had been ages since I...
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Comments (3)
Filed under: Custom IC Design, IC 6.1, Virtuoso, Virtuoso IC 6.1.3
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Functional Verification and EDA "Startups"
By Tom Anderson
on August 25, 2009
A few weeks before DAC, I started working on a blog post about the number of small EDA companies that remain in the functional verification space despite the tough economic times. My interest in completing the entry and publishing on this topic was increased...
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Filed under: DAC, Functional Verification, Open Verification Methodology, OVM, System Verification, verification, Verification methodology
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Comment Direct From XJTAG, Ltd.
By Joseph Hupcey III
on August 24, 2009
Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their trade show strategy -- his message is reproduced in full below. Please post your comments here for the benefit of whole the community, or contact XJTAG apart from this forum...
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Comments (2)
Filed under: DAC, Functional Verification, XJTAG
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Verification Panel: Metrics-Driven Approach Requires Mindset Change
By Richard Goering
on August 24, 2009
Setting up a metrics-driven verification environment isn’t just a matter of tools – it also requires a mindset change along with support from management, according to panelists at the Cadence Ecosystem booth at the Design Automation Conference...
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Filed under: broadcom, Industry Insights, Metric-driven verification, OVM, stmicroelectronics, verilab
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Specman 9.2 Preview: Named Constraints
By Team Specman
on August 21, 2009
[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes Reuven Naveh from Specman R&D to introduce “his” new feature.]...
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Comments (4)
Filed under: AOP, debug, e, Functional Verification, IES-XL, IntelliGen, Specman
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