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Upcoming Webinar: SoC Verification Challenges in the IoT Age

ARM and Cadence host a webinar July 22 to explore how electronics design teams can tackle Internet of Things (IoT) and (SoC) design and verification challenges....  Read More »
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What's Your Summer Engineering Project?

Summer engineering projects can be fun and teach you a lot about yourself you never knew....  Read More »
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EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take" between the EDA world and the many universities around the world....  Read More »
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Whiteboard Wednesdays - Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesdays, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification....  Read More »
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IP Talks! Keynote at DAC 2014—Rethinking Image Processing in SoC Design

Many systems on chip (SoCs) have a "camera block" or image signal processor (ISP) that takes raw data from an image sensor and manipulates that data. But ISPs are moving away from their traditional role and turning into "vision subsystems...  Read More »
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Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online Support

Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40 ) LVS Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files. Videos 2. Mismatch Contribution in Virtuoso Analog Design Environment GXL Mismatch...  Read More »
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Semiconductor Industry Outlook: Enormous Opportunity, Says Jaswinder Ahuja

Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence India, describes the semiconductor industry opportunity in IoT, wearables and mobile applications. ...  Read More »
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Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it...  Read More »
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DAC 2014 Panel: FinFET IC Design Poses No Roadblocks, but Lots of Details

FinFET transistors promise enormous power and performance advantages at process nodes below 20nm, but how will they impact IC design? If you're a digital designer, not much changes - but if you're a custom/analog designer, there's a lot to...  Read More »
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DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com

One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed...  Read More »
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