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Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
SPIE Papers Showcase DFM and Lithography R&D
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 26 2012
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
The Amazing Diversity of the SoC Conference
Although I attend a number of conferences and tradeshows each year, most of these are rather EDA-centric. But last week I was in Irvine for the eighth annual International System-on-Chip (SoC) Conference. It is a fairly small event -- more like a workshop in some ways -- with a single track over its...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Mon, Nov 8 2010
How DRC Plus Makes DFM Easy at 28nm
Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 25 2010
Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp
It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Thu, Apr 29 2010
Logic Design and Test Design: Do they need each other?
Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Sat, Apr 17 2010
Power Management for Test: A Means of Addressing False Failures
Engineering teams are tracing test failures back to IR/voltage drop during test mode. These false failures are impacting yield, profitability. We consider this to be a power management issue for test mode and should be approached as early as front-end design and carried through ATPG and pattern/vector...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Thu, Oct 23 2008
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