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yield,Encounter

  • Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

    3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

    DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 23 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • How DRC Plus Makes DFM Easy at 28nm

    Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 25 2010
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