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virtuoso

  • ASSURA LVS RUN failure: asks OA22.41.010 API

    Hi everyone, I have been struggling with ASSURA LVS, The DRC runs fine however when LVS is run, the following error appears in the error log: Error: failed to initialize OpenAccess because: Requested minor API version '202' which is supported by OpenAccess build '22.41.010' is newer than...
    Posted to Custom IC Design (Forum) by Usama Awais on Sat, Feb 8 2014
  • cdma_2ms_data

    Hi guys In Cadence Virtuoso, you can use the beneficiary pwl files: cdma_2ms_idata.pwl and cdma_2ms_qdata.pwl Could anyone please tell me the specs of the related CDMA, especifically it frequency per channel Thanks a lot, in advance Poltekniko
    Posted to Custom IC Design (Forum) by Politekniko on Tue, Jan 28 2014
  • Pspice model errors in Virtuoso

    Hi Guys I am trying to simulate MAX9643U and EL7202 (using their Pspice models) as a part of my design, in Virtuoso. While I have reviewed many similar problems and solutions in this informative website, I still can not overcome the errors. 1) MAX9643U (the model is available here: http://www.maximintegrated...
    Posted to Custom IC Design (Forum) by Politekniko on Fri, Jan 17 2014
  • Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

    With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series. I know it's been a useful monthly exercise for me. Hopefully it has been helpful for everyone out there as well. Application Notes 1. How to Utilize a Windowing Technique...
    Posted to Custom IC Design (Weblog) by stacyw on Fri, Jan 17 2014
  • finding usage/references/instances of a cell in same/other libraries Virtuoso IC6.1.4.500.12

    Sorry to ask such elementary question but web search didn't turn up anything for us. We have a Virtososo schematic/layout full custom design now with many libraries. Is there some way to see if a particular cell is being instanced in other libraries, and if so, which? This is different than tree...
    Posted to Custom IC Design (Forum) by tdtg on Thu, Jan 16 2014
  • Parasitic extraction of standalone metal traces (IC6.1.5)

    Hi, I have a layout view with multiple metal traces adjacent to one another that I want to simulate as an array of resistors/capacitors. Is there a way to obtain the exact resistance/capacitance of these metal traces through parasitic extraction? I'm assuming there has to be some sort of linking...
    Posted to Custom IC Design (Forum) by Wes8 on Mon, Jan 6 2014
  • Top Cadence YouTube Videos of 2013

    Recognizing that video has become a key tool for explaining new technology, Cadence stepped up its video production in 2013. As a result, there are nearly 400 videos at the Cadence YouTube channel. This blog post provides an introduction to the channel and offers a sampling of some of the videos you'll...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 30 2013
  • Pins, Nets created are not visible

    Hi, As per my understanding, all the data entered in the Cadence Virtuoso tool will get stored in Open Access Database in binary format. My objective is to generate the schematic from the Open Access database APIs. I have created a schematic in which instances, nets and Pins are created using the Open...
    Posted to Custom IC Design (Forum) by Prash123 on Thu, Dec 19 2013
  • Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

    New content on a wide variety of topics in November. Product Information 1. Cadence Online Support Release Highlights Find out about all the new improvements which have been made to the Product Pages on COS. 2. PVE Release Mechanism Change Letter Changes in the way the Physical Verification System (PVS...
    Posted to Custom IC Design (Weblog) by stacyw on Wed, Dec 18 2013
  • Top Ten Cadence Community Blog Posts of 2013

    In 2013, Cadence Community bloggers published over 375 posts in categories including Industry Insights, Functional Verification, Fuller View, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing, in order...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Dec 15 2013
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