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virtuoso,custom/analog
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Virtuoso IC6.1.5
Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, May 13 2013
IBIS model simulation
I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
Posted to
PCB Design
(Forum)
by
niranjan madha
on Wed, Apr 17 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions
10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 12 2013
Virtuoso Advanced Node: Analyzing Layouts Before They’re Done
One paradox of advanced node (28nm and below) custom IC design is that the layout "context" -what is placed near to a device - can change the performance of a device by as much as 30%. Thus, designers must be able to predict layout-dependent effects (LDE) before the final layout is completed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 28 2013
Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Nov 11 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
Things You Didn't Know About Virtuoso: Measurements Across Corners
In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested by many customers--the ability to define a measurement expression which operates on the results of another measurement expression across corners. For example, I can create an expression to measure, say, a delay....
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Feb 9 2012
Things You Didn't Know About Virtuoso: We've Got You Cornered
One of the big buzzwords around the EDA world these days is "variation." Don't you just love buzzwords? Take a perfectly normal, slightly ambiguous word, capitalize it, add a another slightly ambiguous hyphenated suffix, and suddenly you've just solved a new problem for your customers...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Jan 26 2012
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