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virtualization

  • Software-Driven Verification – a Hot Topic for 2013?
    Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 3 2013

  • Virtualization and Simulation Roundtable
    A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that became clear right away is there are way too many...
    Posted to System Design and Verification (Weblog) by jasona on Tue, Oct 13 2009

  • SystemC TLM2 based Virtual Prototype Demo at DVCon
    DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group , and a TLM2 Modeling and Interoperability Tutorial , there's much to learn and contribute at the event. Cadence will have a booth and one of the demos...
    Posted to System Design and Verification (Weblog) by Steve Brown on Tue, Feb 17 2009

  • Virtualization Taxonomy
    I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards doing something (hopefully something interesting...
    Posted to System Design and Verification (Weblog) by jasona on Tue, Oct 28 2008
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