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virtual prototypes

System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system-level design. In May Cadence announced its participation...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Jan 30 2012
One Oil Change and Update my Car to the Latest Software Patch, Please!

Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my interest in the requirements for software and system-level development in automotive applications has grown quite a bit. And after recently having reviewed in previous blog posts requirements for wireless and...

Posted to System Design and Verification (Weblog) by fschirrmeister on Tue, Dec 20 2011
Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create an extensible virtual prototype for the Zynq extensible platform . I have previously written about the need and value for extending virtual platforms at the transaction level . According to the Xilinx Zynq website the...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Nov 21 2011
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 21 2011
Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile. I tend to agree that it does take longer to compile compared to C or Verilog. The primary reason is that SystemC is a somewhat complex set of libraries built on top of C++ and is compiled with g++. Almost every programming...

Posted to System Design and Verification (Weblog) by jasona on Thu, Nov 17 2011
Video: Why TSMC Cares About System-Level Design

Why would TSMC, the world's largest foundry, care enough about electronic system-level (ESL) design to include it in a reference flow? In the short video clip embedded below, Ashok Mehta, senior manager of system verification and software architecture at TSMC, explains why and how his company worked...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 16 2011
Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during the transition from schematic capture to HDLs...

Posted to System Design and Verification (Weblog) by jasona on Fri, Oct 28 2011
Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

You would expect a unique semiconductor product to have a unique software development environment. That is the case with the Xilinx Zynq-7000 family, an Extensible Processing Platform (EPP) that includes a dual-core ARM Cortex-A9 processor and a 28nm FPGA fabric. Today (Oct. 26, 2011) at ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 26 2011
Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual Platforms. Today's article is about how to use a UART as a way to capture logging information about a running system. One of the challenges of developing embedded software is trying to understand what is happening...

Posted to System Design and Verification (Weblog) by jasona on Mon, Oct 24 2011
edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11 th annual edaForum , held in Berlin, Germany. Coming back to my hometown and presenting at this conference was a real treat, even though the traffic was much worse than I remembered, mostly because on that day the Pope visited Berlin. The...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Sep 26 2011

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virtual prototypes

System-Level Design and the Waves of EDA

One Oil Change and Update my Car to the Latest Software Patch, Please!

Will Software Development Cause Another “Industrial” Revolution?

ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

Parallel Compilation for SystemC

Video: Why TSMC Cares About System-Level Design

Welcome to the Zynq-7000 Virtual Platform

Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

edaForum: Evolving Devices from “All in One” to “One for All”