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Video: A Unified Modeling Flow for Virtual Platforms and High-Level Synthesis
Can the same SystemC TLM2 models be used in virtual platforms and high-level synthesis? Today the answer is typically "no." However, there is a "middle ground" modeling methodology that can turn this "no" into a "yes," according to Stuart Swan, senior architect...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 11 2013
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
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by
rgoering
on Wed, Mar 7 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems
The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Feb 23 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
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by
rgoering
on Sun, Jan 22 2012
Why Virtual Platforms Need Advanced Verification
By allowing software development long before silicon is available, virtual platforms (also known as "virtual prototypes" or simply "simulation") are playing an increasingly important role in electronic system development. But they're just an initial step in the next generation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 23 2010
Webinar: Some Practical Advice on Adopting ESL
Changing design methodologies is much like changing the engine of a jet airplane mid-flight, according to David Black, ESL practice lead at XtremeEDA . So what's the best way to step up to electronic system level (ESL) design? The key is developing the right models for the right users, Black said...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 15 2010
Imperas Interview: Connecting Virtual Platforms To HW/SW Verification
Imperas is a provider of virtual platform technology and a member of the new Cadence System Realization Alliance . Imperas has also been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions . Simon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 12 2010
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