Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> virtual protoype
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
virtual protoype
Acceleration
architect
Bring-up
Calypto
CDNLive!
CircuitSutra
CoFluent
Coverage Driven Verification for Embedded Software
co-verification engineer
Co-verification link
C-to-Silicon Compiler
EDA360
embedded software
embedded SW engineer
Embedded Systems Conference
Emulation
ESL
ESL handoff
Fast Models
Hardware/software co-verification
High-Level Synthesis
Imperas
Incisive
Incisive Software Extensions
ip-xact
ISX
Jason Andrews
Jeda
Magillem
Models
Prototyping
QEMU
system C
System Design and Verification
System Design and Verification
System Development Suite
system integration
System Realization
System simulation and analysis
system validation/verification engineer
SystemC
SystemC TLM2
Team ESL
TLM
TLM 2.0
TLM 2.0-driven design
TLM-driven design
TSMC
validation
verification
Verification Acceleration
Verification planning and management
Virtual Platforms
virtual platform
virtual prototype
virtualization
virual platform
XtremeEDA
The Challenge of System Integration and Bring-Up
In the last few years, I have talked with many companies and analysts and consistently heard that system integration time is becoming one of the key challenges in system development. Many companies spend 50% of their total development cycle on system integration and bring-up. This blog will describe...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Tue, May 3 2011
System Realization Webinars in 2010 -- A Summary
Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized internally to align to that vision, and established some great partnerships to help our customers realize their own visions around EDA360. The ED360 vision paper has been well received by both customers and competition...
Posted to
System Design and Verification
(Weblog)
by
MayankBhatia
on Fri, Jan 7 2011
Methodology Is Important But Language Matters - Part 2
In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis, the link to design and implementation is becoming...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Tue, Feb 9 2010
SystemC TLM2 based Virtual Prototype Demo at DVCon
DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group , and a TLM2 Modeling and Interoperability Tutorial , there's much to learn and contribute at the event. Cadence will have a booth and one of the demos...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Tue, Feb 17 2009
Welcome to the "Exploring the Virtual Platform" Series
Today I'm starting a series of articles related to what is commonly called the Virtual Platform or Virtual Prototype. There are probably many definitions of what it means, but I'm going to discuss the Virtual Platform as an abstract software model of a hardware system or subsystem created for...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Jan 16 2009
Page 1 of 1 (5 items)